This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ance...
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ISBN:
(纸本)9781424433391
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim;it brings various improvements e.g., with regard to arrays and other complex data types.
This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-...
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ISBN:
(纸本)9781424433391
This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-to-cell model for both electrical simulation and imaging reconstruction. Preliminary electrical simulations are reported to validate the proposal for Electrical Cell Impedance Spectroscopy (ECIS) applications. The results reported show that low concentration cell culture can be correctly sensed and displayed at several frequencies using the proposed CMOS system.
An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed...
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ISBN:
(纸本)9781509024674
An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.
We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by impl...
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ISBN:
(纸本)9781424433391
We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.
The paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. The developed algorithms are based on the symmetri...
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ISBN:
(纸本)9781424497560
The paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. The developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube, torus, 2-dimensional grid). The achieved results were compared to existing diagnostics algorithms at system level.
In this paper we propose a new deterministic automatic test pattern generator (ATPG) for the stuck- at faults of the combinational representation (CR) of asynchronous sequential digital circuits (ASDCs). The modified ...
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ISBN:
(纸本)9781424466139
In this paper we propose a new deterministic automatic test pattern generator (ATPG) for the stuck- at faults of the combinational representation (CR) of asynchronous sequential digital circuits (ASDCs). The modified FAN algorithm is applied to this CR to generate the test patterns. The FAN was extended to handle the complex gates and to be able to work with the CR of ASDCs. The ATPG was tested over a set of benchmark circuits. The test patterns from the presented ATPG will be used in the future to generate the sequence of test patterns for the ASDCs.
The paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. The Ashenhurst and the Curtis decompositions are considered. The decompositions are executed on Positive Polarization R...
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ISBN:
(纸本)9781424411610
The paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. The Ashenhurst and the Curtis decompositions are considered. The decompositions are executed on Positive Polarization Reed-Muller spectrum of decomposed functions. The elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. The results are very promising.
This paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects ...
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ISBN:
(纸本)9781424411610
This paper(1) tries to find out whether commonly used spot defect fault model is still viable for Deep Sub-Micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.
This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization o...
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ISBN:
(纸本)9781467361361;9781467361354
This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background is presented. Accuracy and time efficiency are demonstrated on a test circuit.
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