This paper presents a scalable asynchronous dataflow processor. The main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other....
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ISBN:
(纸本)1424401844
This paper presents a scalable asynchronous dataflow processor. The main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program.
Due to the high overall complexity of embedded systems in the automotive domain, the concept and system design phases have shown to be important, as they lay the foundations for implementations. Therefore, front-loadi...
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ISBN:
(纸本)9781479945580
Due to the high overall complexity of embedded systems in the automotive domain, the concept and system design phases have shown to be important, as they lay the foundations for implementations. Therefore, front-loading principles are advantageous. In this work, we present a methodology for semi-formal notation based system design. In the end, we demonstrate a transformation scheme for the conversion from system models to executable code, featuring full traceability and support for hardware and software paradigms. An automotive use case demonstrates the capabilities of the outlined approach.
This paper presents the BIST architecture for SOPC circuits. DyRespin reuses scan chains in embedded cores for decompression of highly compressed test vectors. The test access mechanism (TAM) for scan chain connection...
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ISBN:
(纸本)9781424422760
This paper presents the BIST architecture for SOPC circuits. DyRespin reuses scan chains in embedded cores for decompression of highly compressed test vectors. The test access mechanism (TAM) for scan chain connections is implemented as a reconfigurable module. We reuse the switching logic in the interconnection matrix in order to save logic resources. For circuits with higher number of scan chains, the reconfigurable TAM is much more effective than the multiplexer based TAM, comparing usage of the logic resources and clock speeds.
Monitors are small IPs that check critical systems, such as radio-altimeters that on-line control the landing phase in modern planes. It is essential to get correct information and avoid erroneous messages from these ...
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ISBN:
(纸本)9781424466139
Monitors are small IPs that check critical systems, such as radio-altimeters that on-line control the landing phase in modern planes. It is essential to get correct information and avoid erroneous messages from these monitors. Asynchronous monitors are very robust to the environment variations;they remain functional in a wide range of power supplies or temperatures, and can reliably monitor synchronous circuits in a harsh environment. This paper discusses how asynchronous monitors can be modeled and generated from Property Specification Language (PSL). These monitors have been implemented and validated on a FPGA board and a CMOS 65nm technology.
Paper describes suggestions on the improvement of the common On-line structure of the uninterruptable power supply units used for powering of network devices. According to these suggestions a prototype circuit able to...
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ISBN:
(纸本)9781467361361;9781467361354
Paper describes suggestions on the improvement of the common On-line structure of the uninterruptable power supply units used for powering of network devices. According to these suggestions a prototype circuit able to deliver the output power up to 150 W was constructed. The topology was optimized in order maximum efficiency was achieved when the output is fed by an accumulator in order the operating time was as long as possible.
In this paper we present a systematic top-down methodology for designing power-limited and matching-limited circuits with a help of IP database. The presented methodology is a helpful tool for the circuit performance ...
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ISBN:
(纸本)9781424422760
In this paper we present a systematic top-down methodology for designing power-limited and matching-limited circuits with a help of IP database. The presented methodology is a helpful tool for the circuit performance optimization and for the design time shortening. The approach is illustrated on a design of a measuring channel front-end, which senses an external high-voltage signal. The circuit is a signal conditioning front-end for an A/D converter input where the critical design parameters are the power consumption, the matching and the transient response and last but not least the design time. The circuit was implemented in an ASIC and manufactured in 0.35 mu m high-voltage CMOS technology.
A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing th...
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ISBN:
(纸本)9781424497560
A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.
Resilient systems for future application as the Internet of Things (IoT), aerospace or automotive must satisfy demanding specifications over a 10-years lifespan. Thus, time-dependent degradation must be considered in ...
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ISBN:
(纸本)9781538657546
Resilient systems for future application as the Internet of Things (IoT), aerospace or automotive must satisfy demanding specifications over a 10-years lifespan. Thus, time-dependent degradation must be considered in early design stages. To ensure a realistic estimation of degradation impact a whole matrix decomposition algorithm is implemented in a 65nm CMOS technology with different multi threshold voltage standard cells, for a required low-power design. We present an assessment method based on stochastic mission profiles saving at least 10% area and power compared to common methods.
Nowadays in embedded system design it is essential to use Hardware/Software (HW/SW) co-design. This paper is about the development of an autonomic mobile navigation with HW/SW co-design. We managed to design such a sy...
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ISBN:
(纸本)9781424433391
Nowadays in embedded system design it is essential to use Hardware/Software (HW/SW) co-design. This paper is about the development of an autonomic mobile navigation with HW/SW co-design. We managed to design such a system that won the first prize at one of the greatest mars rover competitions in Hungary. The paper demonstrates how to keep the project costs and system design process time low with this methodology. The hardware-software partitioning is discussed in details. This paper is going to deal with the possible and already used technologies in details by emphasizing their advantages.
Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHD...
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ISBN:
(纸本)9781424411610
Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHDL. This paper reports about the various issues dealt with including what topics to cover, text book selection, lab exercises etc. A summary of the students feedback is also included.
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