The directional orientations of leads in the winter ice pack of the Beaufort Sea are studied both spatially and temporally. data from the European Earth Resources Satellite-1 (ERS-1) synthetic aperture radar (SAR) was...
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The directional orientations of leads in the winter ice pack of the Beaufort Sea are studied both spatially and temporally. data from the European Earth Resources Satellite-1 (ERS-1) synthetic aperture radar (SAR) was used. The SAR data was produced in image form at the Alaska SAR Facility (ASF) with 100m/spl times/100m pixel resolution. The lead ice pixels, which included all non-multiyear ice; were defined using a simple thresholding of the radar backscatter values. The orientations of the leads covering the Beaufort Sea during the period of January through March of 1992 were derived using a lead skeletonization technique. Results show a strong temporal persistence in the distribution and orientation of the leads during this period. The orientation of leads newly-formed within a 3-day period were then compared to both the local and large-scale ice deformation fields. Results show a consistent relationship between the orientations of the newly-formed leads and the principal direction of shear within the ice motion fields.< >
Improving initial yield is one way to overcome the ever competitive market of semiconductors. To accomplish this, analyzing particle/pattern defects is a method in finding a countermeasure. We have developed a system,...
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Improving initial yield is one way to overcome the ever competitive market of semiconductors. To accomplish this, analyzing particle/pattern defects is a method in finding a countermeasure. We have developed a system, from controlling the master parameter setting, derive where and what the problem is. It gathers data from QC data; especially related to particles and pattern defects. This system is completely independent from other systems, thus enabling it to be used in any type of line(e.g. unautomated/automated, large/small.)
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, m...
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This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content address memory generates a set of hit signals which identify those positions whose symbols in a specified window are the same as input symbol. These hits signals are then passed to the match logic which determines one matched stream and its match length and location in the window to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB window size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8 /spl mu/m CMOS process technology, clock speed up to 50 MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems.< >
Several fault tolerant scan chain designs are proposed, including the combinational one data flow and two data flow approaches, and the counter based approach. It is shown that these designs have no critical portion, ...
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Several fault tolerant scan chain designs are proposed, including the combinational one data flow and two data flow approaches, and the counter based approach. It is shown that these designs have no critical portion, where a single defect would make the chain inoperative. The yield of these chains is evaluated to show that a long intolerant chain is a predominant yield or harvest detractor, while a tolerant chain becomes an insignificant factor to system yield or harvest.
Time-domain, finite element simulations are used to explore some design issues and the practical modeling envelope for 1-3 composite arrays in underwater pulse-echo imaging transducers. This provides a relatively new ...
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Time-domain, finite element simulations are used to explore some design issues and the practical modeling envelope for 1-3 composite arrays in underwater pulse-echo imaging transducers. This provides a relatively new perspective on the design problem via large-scale 2D and 3D transient simulations that include many piezoelectric pillars within the composite. Cross-talk from a prototype 150 kHz array is modeled and compared to data Some of the composite slab's dispersion behavior is derived from its impulse response and used to interpret cross-talk. Numerical experiments on a 500 kHz design demonstrate effect of pillar taper and distribution-freedoms offered by injection molding. Fourier optics manipulation of the projected acoustic field is illustrated. These studies support an ongoing design and fabrication collaboration under the aegis of United States and Commonwealth naval agencies
This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) discrete cosine transform (VR-DCT), and its VLSI implementation. By mapping the 2-D VR-DCT onto a 2-D ar...
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This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) discrete cosine transform (VR-DCT), and its VLSI implementation. By mapping the 2-D VR-DCT onto a 2-D array of processing elements (PEs), the DCT is efficiently computed with high concurrency and local data exchanges between PEs. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. It has the time complexity of O(N+N/sub NZD//spl middot/log/sub 2/N) for (N/spl times/N) 2-D DCT, where N/sub NZD/ is the number of non-zero digits in the canonic-signed digit (CSD) representation of DCT kernel. Based on the proposed array algorithm, an array processor for (8/spl times/8) 2-D DCT is designed using 1.5 /spl mu/m double metal CMOS technology. From simulation results, it is estimated that (8/spl times/8) 2-D DCT (with N/sub NZD/=4) can be computed in about 0.88 /spl mu/sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels/sec.< >
Supercomputer simulations now can produce multilevel, multi-scalelargedata sets that require new techniques in scientific visualization and higher levels of hardware performance. The authors explore the use virtual ...
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Volume rendering has been proposed as a useful tool for extracting information from largedatasets, where non-visual analysis alone may not be feasible. The scale of these applications implies that data management is ...
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This paper describes a multiresolution approach to the visualization of surface data. The algorithms discussed allow the generation of arbitrary views of 3-dimensional surfaces. Image processing and texture mapping te...
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ISBN:
(纸本)0818649208
This paper describes a multiresolution approach to the visualization of surface data. The algorithms discussed allow the generation of arbitrary views of 3-dimensional surfaces. Image processing and texture mapping techniques are combined in a new 3-pass scanline algorithm to achieve smooth and continuous translations, rotations and scale changes of largedata sets. The implementations of the algorithms on a massively parallel SIMD video supercomputer, the Princeton Engine, allows the scenes to be generated interactively at video rates.
The analysis of program performance on massively parallel (MPP) systems is a non-trivial task which is increasingly performed using visualization tools. Conventional processing, analysis, and display methods typically...
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