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共 4895 条记录，以下是4831-4840 订阅

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Robustizing circuit optimization using Huber functions

Robustizing circuit optimization using Huber functions

引用

Microwave, MTT-S International symposium

作者： J.W. Bandler S.H. Chen R.M. Biernacki K. Madsen L. Gao H. Yu Optimization Syst. Associates Inc. Dundas Ont. Canada Simulation Optimization Systems Research Laboratory Department of Electrical and Computer Engineering McMaster University Hamilton Canada Institute of Numerical Analysis Technical University of Denmark Lyngby Denmark Department of Mathematics and Institute of Mathematics Peking University Beijing China

The authors introduce a novel approach to 'robustizing' microwave circuit optimization using Huber functions, both two-sided and one-sided. They compare Huber optimization with l/sub 1/, l/sub 2/, and minimax methods in the presence of faults, large and small measurement errors, bad starting points, and statistical uncertainties. They demonstrate FET statistical modeling, multiplexer optimization, analog fault location, and data fitting. They extend the Huber concept by introducing a 'one-sided' Huber function for large-scale optimization. For large-scale problems, the designer often attempts, by intuition, a preliminary optimization by selecting a small number of dominant variables. It is demonstrated, through multiplexer optimization, that the one-sided Huber function can be more effective and efficient than minimax in overcoming a bad starting point.< >

关键词： Robustness Circuit optimization Minimax techniques Multiplexing large-scale systems Optimization methods Circuit faults Measurement errors Microwave FETs Fault location

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A two-pole circuit model for VLSI high-speed interconnection

A two-pole circuit model for VLSI high-speed interconnection

引用

ieee International symposium on Circuits and Systems (ISCAS)

作者： D. Zhou S. Su F. Tsui D.S. Gao J.S. Cong EE Department UNC-Charlotte Charlotte NC USA Sun MicroSystems Inc.orporated Mountain View CA USA Cs Deptartment UCLA Los Angeles CA USA

A high-speed VLSI interconnection is modeled by using a generic distributed-RLC tree. Through a detailed analysis of the distributed-RLC tree a two-pole approximation system is established. Relating the solution of the two-pole approximation to the interconnection geometric parameters, a VLSI performance-driven layout problem is formulated which reveals the interplay between the interconnection performance and its geometrical parameters.< >

关键词： Very large scale integration Integrated circuit interconnections RLC circuits Distributed parameter circuits Capacitance Impedance Performance analysis Integrated circuit modeling Tree data structures Wire

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A quantitative risk assessment method for space flight software systems

A quantitative risk assessment method for space flight softw...

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International symposium on Software Reliability Engineering (ISSRE)

作者： A.T. Lee T.R. Gunn NASA Houston TX USA Loral Space Information Systems Houston TX USA

A risk index factor has been developed at the NASA Johnson Space Center in order to quantify the risk associated with individual software components in programs developed for space flight applications. Risk can be defined as the combination of the likelihood of a failure occurrence with the consequence of that occurrence. The risk index attempts to quantify this product, utilizing the results from software complexity analysis, the evaluation of test coverage, and a failure modes and effects analysis. This report presents an overview of the development of the risk index factor as well as the methodology used in performing the support analyses. Results from the data collected for two dissimilar space flight projects are also presented.

关键词： Risk management Software systems Risk analysis Software testing Failure analysis Application software Software maintenance NASA Performance analysis large-scale systems

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Designing a coprocessor for recurrent computations

Designing a coprocessor for recurrent computations

引用

International symposium on Parallel and Distributed Processing (IPDPS)

作者： K.N. Ganapathy B.W. Wah Coordinated Science Laboratory Urbana IL USA

We present the design of an application-specific coprocessor for algorithms that can be modeled as uniform recurrences or "uniformized" affine recurrences. The coprocessor has a regular array of processors connected to an access-unit for intermediate storage of data. The distinguishing feature of our approach is that we assume the coprocessor to be interfaced to a standard, slow (single-ported) memory with low bandwidth. Hence, good performance is achieved by effectively exploiting data locality in the applications by the compiler, and the final architecture is chosen by a tradeoff analysis driven by the mapping process. Preliminary results indicate that the coprocessor has significantly lower clock rates or higher performance than that of existing RISC processors and is cost-effective for executing loop computations.< >

关键词： Coprocessors Costs Very large scale integration Application software Hardware Computer architecture Performance analysis Clocks Pipeline processing Acceleration

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Architecture and VLSI design of a VLSI neural signal processor

Architecture and VLSI design of a VLSI neural signal process...

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ieee International symposium on Circuits and Systems (ISCAS)

作者： U. Ramacher J. Beichter N. Bruls E. Sicheneder Siemens AG Corporation Research and Development Munich Germany

A chip based on a scalable parallel systolic VLSI architecture has been designed for executing the compute-bound algorithmic primitives used by search and learning algorithms in neural networks and low level signal processing. The signal processor executes the algorithmic primitives and shared by all neural nets. The throughput is 800 million connection/s (1C = 16 bit) at 50 MHz. The chip contains 610 K transistors at 187 mm/sup 2/ in a 1.0-/spl mu/m CMOS technology. The I/O bandwidth for the weights is 3.2 Gbit/s and total data bandwidth is 10.9 Gbit/s. The processor is also useful for low-level signal preprocessing.< >

关键词： Very large scale integration Signal design Signal processing Signal processing algorithms Computer architecture Neural networks CMOS technology Bandwidth Algorithm design and analysis Computer networks

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Time- and order-recursive estimation of higher order moments in a linear array

Time- and order-recursive estimation of higher order moments...

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ieee International symposium on Circuits and Systems (ISCAS)

作者： H.M. Stellakis E.S. Manolakos Communications and Digital Signal Processing Center Department of Electrical and Computer Engineering Northeastern University Boston MA USA

To achieve real-time performance in signal processing applications that require the adaptive estimation of higher order statistics, it is necessary to (a) design new time-recursive algorithms and (b) introduce parallel processing and pipelining. Time-recursive estimation methods of the computation of the higher order moments from the incoming sampled data are presented. The fixed size sliding window estimation algorithm is mapped onto an optimal linear array. The array provides estimates of all the moments up to the fourth order in time- and order-recursive fashion, achieves minimum latency and is suitable for VLSI implementation. A systematic synthesis methodology facilitates the construction of the optimal locally recursive algorithm and the design of the architecture.< >

关键词： Signal processing algorithms Algorithm design and analysis Adaptive signal processing Adaptive estimation Higher order statistics Signal design Parallel processing Pipeline processing Delay Very large scale integration

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Satellite image processing using cellular array processor (CAP)

Satellite image processing using cellular array processor (C...

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ieee International symposium on Geoscience and Remote Sensing (IGARSS)

作者： M. Ajiro H. Miyata T. Kan M. Ono ERSDAC Data Center Tokyo Japan Computer and Information Systems Laboratory Mitsubishi Electric Corporation Limited Kamakura Japan Kamakura Works Mitsubishi Electric Corporation Limited Kamakura Japan

Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the Earth for various studies, including the investigation of Earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper describes the structure of the ERSDIS and the details of the CAP design.< >

关键词： Satellites Image processing Earth Image storage Automatic control Information systems Parallel processing Optical sensors Microwave sensors data analysis

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High-performance data systems

High-performance data systems

引用

11th ieee symposium on Mass Storage Systems

作者： Collins, Bill Los Alamos Nat Lab NM USA

ISBN: (纸本)0818621559

It is noted that advances in massively parallel, large-memory computers and cooperative processing networks allow researchers to execute large-scale codes that generate massive amounts of data. Recent developments in high-speed networks allow large amounts of data to be transferred through a HiPPI (High Performance Parallel Interface) network in reasonable time frames. To support this high-performance computing environment, data storage, and data conversion capabilities must be provided to allow the massive amounts of data generated to be stored in a timely and reliable manner and to allow them to be retrieved easily for analysis and display.

关键词： Computers, Supercomputer

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Application of time-frequency and time-scale analysis to underwater acoustic transients

Application of time-frequency and time-scale analysis to und...

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1992 ieee-SP International symposium on Time-Frequency and Time-scale analysis

作者： Brotherton, T. Pollard, T. Barton, R. Krieger, A. Marple, L. Orincon Corp. 9363 Towne Centre Dr. San DiegoCA92121 United States Orincon Corp. 10015 Old Columbia Road ColumbiaMD21046 United States

ISBN: (纸本)0780308050

Underwater acoustic transients from man-made structures and biologics are very rich in structure and detail, very diverse in terms of duration, highly nonstationary, and often mixed with multipath. Orincon has an ongoing program to f i d algorithmic analysis techniques that can extract features of these transients for purposes of high confidence classification. It has been found that no one analysis technique can adequately capture features from all the possible transient classes that we have in a large data base of actual transients. Presented here are side-by-side comparisons of numerous time-frequency and time-scale representations of an unclassified acoustic transients. The techniques illustrated include the Short-Time Fourier Transform (STFT) tuned to different analysis bandwidths, the Gabor - Wavelet Time-scale Representation (TSR), the Double Diamond (DD) TFR, the Adaptive Optimal Radially Gaussian Kernel (AOK) TFR. and model based TFRs. The strengths and weaknesses of the various analysis representations are discussed. © 1992 ieee.

关键词： Underwater acoustics

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'Physiological' time in the analysis and modelling of real and artificial neural nets

'Physiological' time in the analysis and modelling of real a...

引用

1992 RNNS/ieee symposium on Neuroinformatics and Neurocomputers, RNNS 1992

作者： Vladimirsky, B.M. Vladimirsky, B.B. A. B. Kogan Research Institute for Neurocybernetics Rostov State University 194/1 Stachka Avenue Rostov-on-Don344104 Russia

ISBN: (纸本)0780308093

It is proposed that existing neurobiological data on the properties of single nerve cells and of the systems formed by them will allow, when reproduced in models, a new paradigm of the functioning of neuronal nets, based on the inner time scale concept to be introduced. The concept of inner (physiological) time provides a new approach to modeling processes in neuronal networks. Different inner time scales may be associated with different coordinate systems, and decomposition into coordinates may allow one to extract various invariant measures from the input information. It is noted that in the case of the description of neuronal network behavior in terms of phase packages the time variable is not explicitly present at all, whereas in the case of using stability theory techniques, it is interesting to analyze the process dynamics on a large time scale. © 1992 ieee.

关键词： Neurons

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