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Brief Industry Paper: Workload-Aware GPU Performance Estimation in the Airborne embedded System 27

Brief Industry Paper: Workload-Aware GPU Performance Estimat...

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30th ieee International symposium on Software Reliability Engineering (ISSRE)

作者： Yao, Yuan Wu, Sikai Liu, Shuangyang Sun, Qingshuang Yang, Gang Hu, Yujiao Zhang, Yu Liu, Huixia Tian, Xinyu Northwestern Polytech Univ Sch Comp Sci Xian Peoples R China Xian Aisheng Technol Grp Co Ltd Dept Command & Control Xian Peoples R China Xian Aisheng Technol Grp Co Ltd Dept Aviat Elect Xian Peoples R China

ISBN: (纸本)9781665403863

New generation airborne embedded system has deployed Graphical Processing Units (GPUs) to raise processing capability to meet growing computational demands. applications in the airborne embedded system have strict real-time constraints. Therefore, it is necessary to accurately predict timing behaviors of those applications. Many previous work propose GPU performance models to estimate the execution time of applications. However, most of those models do not consider the impact of co-execution on the GPU performance. In this paper, we propose a workload-aware GPU performance model to predict the execution time of applications executed concurrently on a single GPU. Experimental results illustrate that the proposed model can achieve a 5.1%-11.6% prediction error in a real airborne embedded hardware platform.

关键词： GPU performance model GPU workload Airborne embedded system Self-organization fuzzy neural network

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Mission Profile Emulator for Sub-modules in CHB-BESS of Frequency Support applications 15

Mission Profile Emulator for Sub-modules in CHB-BESS of Freq...

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ieee 15th International symposium on Power Electronics for Distributed Generation Systems (PEDG)

作者： Wang, Moxi Tan, Lingqi Ma, Ke Shanghai Jiao Tong Univ Dept Elect Engn Shanghai Peoples R China Guangdong Power Grid Co Ltd Elect Power Res Inst Guangzhou Peoples R China

ISBN: (纸本)9798350361018;9798350361001

The integration of large-scale renewable sources presents significant challenges to the frequency stability of the power grid. Battery energy storage (BES) represents a promising technology for providing short- to medium-term frequency support. However, advanced control strategies for frequency support make it complex for the transient process within the power circuit and battery clusters. These complexities can result in adverse transient mission profiles, leading to complex electrical-thermal stresses on the power components and batteries. This paper proposes a control structure for the mission profile emulator (MPE), which is designed to simulate the transient behavior of sub-modules (SMs) in cascaded H-bridge converter-based battery energy storage system (CHB-BESS) of frequency support applications. The controller incorporates a virtual model that generates reference signals for the MPE in real time. The grid behavior and control strategy of frequency support are included in the virtual model to reproduce authentic transient mission profiles. The effectiveness of the proposed test scheme is validated through simulations with PLECS and down-scale experiments.

关键词： mission profile emulator (MPE) frequency support cascaded H-bridge converter-based battery energy storage system (CHB-BESS) sub-module (SM) reliability

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Advanced Modeling and Analysis of Individual and Combined TSN Shapers in OMNeT++ 29

Advanced Modeling and Analysis of Individual and Combined TS...

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29th ieee International Conference on embedded and real-time Computing Systems and applications, RTCSA 2023

作者： Debnath, Rubi Hortig, Philipp Zhao, Luxi Steinhorst, Sebastian TUM School of Computation Information and Technology Technical University of Munich Germany Beihang University Beijing China

ISBN: (纸本)9798350337860

The selection of a time-Sensitive Networking (TSN) shaping mechanism is a crucial design decision that impacts the Quality of Service (QoS) of applications and configuration complexity. However, current research has mainly evaluated TSN shapers individually, despite them being designed to work together in an egress port. Hence, the lack of investigation of the mixed TSN shaping mechanism is a major limitation of the current state of the art. Combined TSN traffic shaping provides greater flexibility to improve QoS than individual shapers, making it particularly beneficial for real-time applications. This paper aims to bridge this research gap by implementing the Asynchronous Traffic Shaper (ATS) in a plug-and-play manner, enabling its use individually or in combination with other TSN shapers. We propose various models of mixed TSN shaper architectures and implement the frozen and non-frozen credit behavior of the time Aware Shaper (TAS) + Credit Based Shaper (CBS) during the guard band (GB) using OMNeT++. Furthermore, we compare the simulation results of ATS and CBS with the Network Calculus (NC) upper bounds. Our results indicate that the simulated delays (SMDs) were significantly lower than the theoretical worst-case delays (WCDs) obtained from the NC, indicating the need for tighter theoretical upper bounds, particularly for higher network loads. To the best of our knowledge, we are the first to provide simulation-based performance analysis of the combined TAS+ATS+CBS and TAS+ATS+Strict Priority (SP) architecture. Overall, this paper highlights the benefits of combining TSN shapers and encourages further research into the potential advantages of utilizing multiple shapers simultaneously to decrease reliance on TAS and CBS. © 2023 ieee.

关键词： Quality of service

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How Fast is My Software? Latency Evaluation for a ROS 2 Autonomous Driving Software 34

How Fast is My Software? Latency Evaluation for a ROS 2 Auto...

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34th ieee Intelligent Vehicles symposium (IV)

作者： Betz, Tobias Schmeller, Maximilian Teper, Harun Betz, Johannes Tech Univ Munich Inst Automot Technol TUM Sch Engn & Design D-85748 Garching Germany Tech Univ Munich TUM Sch Computat Informat & Technol D-85748 Garching Germany Tech Univ Dortmund Inst Design Automat Embedded Syst D-44227 Dortmund Germany Tech Univ Munich TUM Sch Engn & Design Autonomous Vehicle Syst D-85748 Garching Germany

ISBN: (纸本)9798350346916

Violations of real-time properties and high latencies have emerged as crucial issues in autonomous vehicles since they can lead to unwanted vehicle behavior and critical maneuvers. Our study aims to provide a comprehensive understanding of latencies in a software stack for autonomous vehicles. In this paper, we present an evaluation workflow to inspect software and the occurring latencies for ROS 2 applications. This workflow was used to analyze the open-source autonomous driving stack *** by showing the influence of different soft- and hardware configurations. Our focus is on the evaluation of end-to-end, communication, computation, and idle latencies. Based on the results, we show the bottlenecks and motivate future directions to optimize ROS 2 autonomous driving software.

关键词： Autonomous vehicles

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Uni-Render: A Unified Accelerator for real-time Rendering Across Diverse Neural Renderers 31

Uni-Render: A Unified Accelerator for Real-Time Rendering Ac...

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31st ieee International symposium on High Performance Computer Architecture, HPCA 2025

作者： Li, Chaojian Li, Sixu Jiang, Linrui Zhang, Jingqun Lin, Yingyan Celine Georgia Institute of Technology United States

ISBN: (纸本)9798331506476

Recent advancements in neural rendering technologies and their supporting devices have paved the way for immersive 3D experiences, significantly transforming human interaction with intelligent devices across diverse applications. However, achieving the desired real-time rendering speeds for immersive interactions is still hindered by (1) the lack of a universal algorithmic solution for different application scenarios and (2) the dedication of existing devices or accelerators to merely specific rendering pipelines. To overcome this challenge, we have developed a unified neural rendering accelerator that caters to a wide array of typical neural rendering pipelines, enabling real-time and on-device rendering across different applications while maintaining both efficiency and compatibility. Our accelerator design is based on the insight that, although neural rendering pipelines vary and their algorithm designs are continually evolving, they typically share common operators, predominantly executing similar workloads. Building on this insight, we propose a reconfigurable hardware architecture that can dynamically adjust dataflow to align with specific rendering metric requirements for diverse applications, effectively supporting both typical and the latest hybrid rendering pipelines. Benchmarking experiments and ablation studies on both synthetic and real-world scenes demonstrate the effectiveness of the proposed accelerator. It achieves real-time rendering speeds (> 30 FPS) and up to 119 × speedups over state-of-the-art neural rendering hardware across varied rendering pipelines, while adhering to power consumption constraints of around 5 W, typical for edge devices. Consequently, the proposed unified accelerator stands out as the first solution capable of achieving real-time neural rendering across varied representative pipelines on edge devices, potentially paving the way for the next generation of neural graphics applications. © 2025 ieee.

关键词： Reconfigurable architectures

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2023 ieee Sensors applications symposium, SAS 2023 - Proceedings

2023 IEEE Sensors Applications Symposium, SAS 2023 - Proceed...

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18th ieee Sensors applications symposium, SAS 2023

ISBN: (纸本)9798350323078

The proceedings contain 103 papers. The topics discussed include: robustness investigation of a particle analyzer for the analysis of volcanic ash;identification of cooking ADL actions through analysis of thermal camera video;designing and developing a mobile application for monitoring & visualizing blood pressure data;automatic real-time fever screening in a thermal video surveillance system;reducing fixation error due to natural head movement in a webcam-based eye-tracking method;depth sensor application in ground unevenness estimation for UAV emergency landing;an embedded multi-sensor architecture for applications in structural health monitoring;a high-speed stereo monitoring system for remote one-man operation;studying the effects of clutter using v-band radar for drone classification;and systematic sensor data-driven analysis pipeline for anomaly monitoring of bridges and rails.

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SSFuzz: State Sensitive Fuzzing for Network Protocol Implementations 22

SSFuzz: State Sensitive Fuzzing for Network Protocol Impleme...

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22nd ieee International symposium on Parallel and Distributed Processing with applications, ISPA 2024

作者： Cai, Chengnuo Zhou, Lei Yu, Bo National University of Defense Technology School of Computer China

ISBN: (纸本)9798331509712

Protocol implementations are stateful and reactive systems, where the protocol process communicates with the client through a session. Complex state changes of implementations limit the efficiency of fuzzing. Current methods typically send a mutated message sequence to the protocol implementation, then terminate the session and evaluate the message sequence based on the feedback. We observe the following issues: (1) The state changes of the protocol implementation are random because of mutated messages, and message schedule methods that do not consider the real-time state of the target are blind;(2) The value of a message can vary significantly in different states, making seeds value evaluation method based on the entire message sequence insufficiently precise. (3) Existing fuzzing approaches actively terminate sessions after a test, resulting in resource *** solve these problem, we propose SSFuzz, a state sensitive fuzzing approach for protocol implementations. First, it monitors the state transitions and path feedback of the protocol implementation in real-time. Second, it dynamically schedules messages based on real-time state transitions during testing. According to the state transitions and path feedback after processing a message, it then conducts more precise evaluation of the messages. Last, we achieve testing multiple states within one session by reusing session. We believe that our approach better adapts to the characteristics of protocol implementations. We validated our approach on 9 widely used protocol implementations from ProFuzzBench. Compared to the state-of-the-art network protocol greybox fuzzing tool AFLnet, SSFuzz can increase discovered branch coverage on average 1.31% and discovers 25.28% more unique crashes within 24 hours. © 2024 ieee.

关键词： Internet protocols

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An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems 28

An Adaptive Strategy for Dynamic Resource Allocation and Sch...

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28th International symposium on VLSI Design and Test, VDAT 2024

作者： Paul, Suraj Indian Institute of Engineering Science and Technology Dept. of Information Technology West Bengal India

ISBN: (纸本)9798350380101

Workloads on multicore platforms are increasingly becoming dynamic. Resource assignment decisions of applications impact their timing response and system performance, especially for Network-on-Chip (NoC) based multicore systems hosting real-time applications. Such systems offer better scope for parallel application execution. Design-time solutions for task allocation may not be suitable for dynamic workloads. In such scenarios, dynamic task allocation techniques give improvement in system resource utilization and lends adaptivity to changing application workload. This work presents an efficient and scalable adaptive technique for joint allocation and scheduling of tasks of mixed critical applications at runtime. Potential allocation solutions are explored at design-time by focusing on timing characteristics of applications and their communication energy consumption while considering a set of multitasking processors. These design-points are reconfigured dynamically at runtime for adapting the resource allocation decisions of multiple applications depending on platform resources and application requirements. Simulation results demonstrate that the proposed strategy achieves 20.4% and 33.5% improvement in communication energy consumption and timing satisfaction of tasks of allocated applications, respectively. Also, the run-time overhead of online reconfiguration reduces by 27.8% with respect to the existing dynamic resource allocation approaches. © 2024 ieee.

关键词： Multitasking

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Enhancing Automotive embedded applications: A Comprehensive Evaluation of Control Flow Checking Methods

Enhancing Automotive Embedded Applications: A Comprehensive ...

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2024 ieee International Conference on Design, Test and technology of Integrated Systems, DTTIS 2024

作者： Solouki, Mohammadreza Amel Sini, Jacopo Violante, Massimo Politecnico di Torino Department of Control and Computer Engineering Turin Italy

ISBN: (纸本)9798350363128

Mitigating the risks posed by Random Hardware Failures (RHFs) is crucial to prevent data corruption and Control Flow Errors (CFEs) in embedded systems. This paper addresses these concerns through the application of Software-Implemented Hardware Fault Tolerance (SIHFT) methods, emphasizing compatibility with high-level programming languages such as C. Current SIHFT methods, often implemented in low-level Assembly, present challenges in terms of overhead to code size and real-time execution. Our proposed approach focuses on pre-compilation application of SIHFT methods, specifically Control Flow Checking (CFC), to identify CFEs within C-language-based code. We conducted a comparative analysis of two established software-based CFE detection methods in C, seamlessly integrating CFC methods into the application behavioral model. Our methodology ensures ISO26262 compliance, crucial for the automotive sector, offering a software-only strategy that aligns with safety and cost considerations. © 2024 ieee.

关键词： C (programming language)

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A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for real time applications 2

A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog H...

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2nd ieee International Conference on Device Intelligence, Computing and Communication Technologies, DICCT 2024

作者： Himanshu Charan, Chaagan School of Vlsi & Embedded System National Institute of Technology Kurukshetra India National Institute of Technology Department of Electronics & Communication Engineering Kurukshetra India

ISBN: (数字)9798350372847

ISBN: (纸本)9798350372847

Modern CPUs are operating faster than ever because to the quick development of integrated circuits. On hardware, FIFO frequently acts as the buffer for data transmission and reception. In order to transfer data across systems with various time domains quickly and simply, asynchronous FIFOs can solve a variety of clock domain difficulties. However, stable operation of the system requires adjustment of the clock periods. This paper focuses on making the use of two '2 D Flip flop' as synchroniser to avoid the metastability conditions in the design. Universal gates and status flags have been introduced with Gray Code to increase the speed and efficiency of FIFO. It is anticipated that this paper will serve as a resource for IC designers when they are creating interface circuits and helpful in real time applications as it happens on own time and doesn't need scheduling includes emails, company newsletter, chatting on Slack, and Asana and Trello boards. The results have been verified using the software Xilinx Vivado that the proposed asynchronous design is relatively faster, accurate and consumes relatively lesser power while maintaining comparable performance in terms of delays and metastability. The design presented here is for a 16-bytes FIFO memory which can be modified further as per the memory required. © 2024 ieee.

关键词： Clocks

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