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检索条件"任意字段=IEEE Symposium on Real-Time and Embedded Technology and Applications"

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real-time corner detection algorithm based on GPU

Real-time corner detection algorithm based on GPU

引用

作者： Huang, Xueyu Wu, Qifeng Jiangxi University of Science and Technology Ganzhou China

ISBN: (纸本)9780769543604

This paper presents a class of GPU-based real-time corner detection algorithms. On the basis of existing corner detection algorithms, GPU-based real-time corner detection algorithms are executed by GPU. To further improve the speed of the algorithm, the algorithm uses the method of corner value map compression. Experiments show that the GPU-based real time corner detection algorithm is suited to the real-time applications with resolution up to 1024 * 768 pixels. © 2010 ieee.

关键词： Graphics processing unit

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GPRS-based fault monitoring for distribution grid

GPRS-based fault monitoring for distribution grid

引用

2010 ieee/ASME International Conference on Mechatronic and embedded Systems and applications, MESA 2010

作者： Tie, Zhi Xin Wang, Zhao Qing Instructional Division of Computer Technology Zhejiang Sci-Tech University Hangzhou Zhejiang 3100 IS China

ISBN: (纸本)9781424471010

The GPRS is a useful mean to solve the communication problem in the automatic system of power distribution network system. This paper designs a GPRS-based real-time system to monitor the on-off states of the switching station in the power distribution system. The system is consisting of a low-power controller of MSP430F149, the module of GR64 from WAVECOM company and detection circuits of on-off states. The IEC60870-5-101 protocol is used in the system. Therefore, it can conveniently communicate with other SCADA systems. It is reliable and stable running on site. © 2010 ieee.

关键词： SCADA systems

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On formal modeling of TOPPERS embedded software

On formal modeling of TOPPERS embedded software

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8th International Conference on Software Engineering Research, Management and applications, SERA 2010

作者： Kawabe, Yoshinobu Ito, Nobuhiro Ishii, Naohiro Aichi Institute of Technology 1247 Yachigusa Yakusa-cho Toyota-shi Aichi 470-0392 Japan

ISBN: (纸本)9780769540757

Today embedded software is widely used. As the complexity of embedded systems grows, the number of tasks performed by embedded software is increasing. These tasks must communicate with each other to achieve synchronization. And therefore, the growing complexity of communications is making it increasingly difficult to program and debug these tasks. To confirm the correctness of embedded software, this paper introduces a formal specification language for embedded systems that can deal with their concurrent nature. After formalizing the APIs of an embedded real-time operating system, we demonstrate how to describe and verify embedded software formally. © 2010 ieee.

关键词： Specification languages

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SESAM: An MPSoC simulation environment for dynamic application processing

SESAM: An MPSoC simulation environment for dynamic applicati...

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10th ieee International Conference on Computer and Information technology, CIT-2010, 7th ieee International Conference on embedded Software and Systems, ICESS-2010, 10th ieee Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Ventroux, N. Guerre, A. Sassolas, T. Moutaoukil, L. Blanc, G. Bechara, C. David, R. Embedded Computing Laboratory CEA LIST Gif-sur-Yvette F-91191 France

ISBN: (纸本)9780769541082

Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this paper, we present an asymmetric MPSoC simulator environment, named SESAM. This tool can be used for the architecture exploration and optimization, and the design of a complete MPSoC solution for dynamic application processing. Its performances and capabilities are demonstrated through a complete MPSoC platform and an implementation of the component labeling algorithm. © 2010 ieee.

关键词： Energy utilization

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Fixed-Priority Multiprocessor Scheduling with Liu and Layland's Utilization Bound

Fixed-Priority Multiprocessor Scheduling with Liu and Laylan...

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ieee symposium on real-time and embedded technology and applications

作者： Nan Guan Martin Stigge Wang Yi Ge Yu Department of Computer Science and Technology Northeastern University China Department of Information Technology University of Uppsala Sweden

Liu and Layland discovered the famous utilization bound for fixed-priority scheduling on single processor systems in the 1970's. Since then, it has been a long standing open problem to find fixed-priority scheduling algorithms with the same bound for multiprocessor systems. In this paper, we present a partitioning-based fixed-priority multiprocessor scheduling algorithm with Liu and Layland's utilization bound.

关键词： Processor scheduling Scheduling algorithm real time systems Multiprocessing systems Application software Information technology Computer science Partitioning algorithms Testing H infinity control

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Multi-Module Synchronic Data Acquisition Based on T-CLK

Multi-Module Synchronic Data Acquisition Based on T-CLK

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5th ieee Conference on Industrial Electronics and applications

作者： Xu, Ke Zhao, Zhiwen Jiang, Sisi Mou, Sheng Wang, Feng Beijing Normal Univ Dept Elect Sch Informat Beijing 100875 Peoples R China

ISBN: (纸本)9781424450466

For the practical application of synchronous acquisition of digital signals on many kinds of circuit boards, this paper, based on NI-TCLK (Trigger clock) synchronization technology, the modular hardware as the circuit board based on PXI (PCI extensions for Instrumentation) bus, as well as the modular software as NI-LABVIEW, a multi-module synchronic data acquisition system is developed. Accordingly, the multi-module digital signals can be acquired simultaneously, displayed as well as stored in a NI embedded computer platform. With the use of the clock on PXI backplane, NI-TCLK technology etc., this system makes a very good solution to the problem of synchronization between multiple circuit boards. The experiment results shows that the system's real-time performance can be well satisfied, the timing relationships between signals can be clearly shown in figures and the requirements of synchronization for multi-module data acquisition can be achieved in the system.

关键词： Data acquisition T-CLK technology Timing and synchronization PXI modular platform LABVIEW

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A FPGA/DSP Design for real-time Fracture Detection Using Low Transient Pulse

A FPGA/DSP Design for Real-Time Fracture Detection Using Low...

引用

ieee International symposium on Industrial Electronics (ISIE)

作者： Mathur, Akash Chang, Timothy N. New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA

ISBN: (纸本)9781424463916

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation utilizes two microelectronics technologies: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The DSP carries out the analysis of the received signal at a much lower rate hence can accommodate a large number of signal channels. The FPGA runs at a higher frequency (62.5MHz) to generate the LTP signal and to calculate the envelope of the received signal (sampled at 1MHz). This research elaborates on designing a Quadrature AM (QAM) demodulator on the FPGA for the received signal from the ultrasound and for the detection of the presence of edges/fracture on the test materials. The complete system is designed and optimized in a high level Matlab\Simulink fixed point simulation. Different sub-blocks are then implemented and optimized on the FPGA where efforts are taken to maintain its accuracy with the simulated model. In this work, the technology is applied to determine the location of the Saw bone plate edges based on the received signals which are then passed through a QAM demodulator in the FPGA and a peak detector in the DSP to calculate the echo peak times.

关键词： MatlabSimulink Sawbone plate edge demodulators design engineering digital signal processing chips digital signal processor design echo peak time field programmable array design field programmable gate arrays fracture logic design low transient pulse mathematics computing peak detector peak detectors plates (structures) quadrature AM demodulator quadrature amplitude modulation real-time fracture detection ultrasonic applications ultrasound signal

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Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA

Mapping real-life applications on run-time reconfigurable No...

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2010 International Conference on Field-Programmable technology, FPT'10

作者： Singh, Amit Kumar Kumar, Akash Srikanthan, Thambipillai Ha, Yajun School of Computer Engineering Nanyang Technological University Singapore Singapore Department of Electrical and Computer Engineering National University of Singapore Singapore Singapore

ISBN: (纸本)9781424489817

Multiprocessor systems-on-chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. These MPSoCs are employing Network-on-Chip (NoC) for reasons of efficiency and scalability. Additionally, these systems need to support run-time reconfiguration of their components to cater to dynamically changing demands of the system. Designing and programming such systems for real-life applications prove to be a major challenge. This paper demonstrates the designing of reconfigurable NoC-based MPSoC and programming it for real-life applications. The NoC is reconfigured at run-time to support different combinations of multiple applications at different times. The platform is verified with a case study executing the parallelized C-codes of a simple producer-consumer and JPEG decoder applications on a NoC-based MPSoC on a Xilinx FPGA. Based on our investigations to map the applications on a 3×3 platform, we show that the NoC reconfiguration overhead is kept at a minimum and the platform utilizes 85% of the total available slices of Virtex-5 FPGA. Moreover, we show that the proposed approach is highly scalable when targeting for large number of applications. © 2010 ieee.

关键词： Network-on-chip

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Predictive and dynamic resource allocation for enterprise applications

Predictive and dynamic resource allocation for enterprise ap...

引用

作者： Al-Ghamdi, M. Chester, A.P. Jarvis, S.A. Department of Computer Science University of Warwick Coventry United Kingdom

ISBN: (纸本)9780769541082

Dynamic resource allocation has the potential to provide significant increases in total revenue in enterprise systems through the reallocation of available resources as the demands on hosted applications change over time. This paper investigates the combination of workload prediction algorithms and switching policies: the former aim to forecast the workload associated with Internet services, the latter switch resources between applications according to certain system criteria. An evaluation of two well known switching policies - the proportional switching policy (PSP) and the bottleneck aware switching policy (BSP) - is conducted in the context of seven workload prediction algorithms. This study uses real-world workload traces consisting of approximately 3.5M requests, and models a multi-tiered, cluster-based, multi-server solution. The results show that a combination of the bottleneck aware switching policy and workload predictions based on an autoregressive, integrated, moving-average model can improve system revenue by as much as 43%. © 2010 ieee.

关键词： Switching

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Usage of the safety-oriented real-time OASIS approach to build deterministic protection relays

Usage of the safety-oriented real-time OASIS approach to bui...

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5th International symposium on Industrial embedded Systems, SIES 2010

作者： Jan, Mathieu David, Vincent Lalande, Jimmy Pitel, Maurice CEA LIST Embedded Real Time Systems Laboratory Point Courrier 94 Gif-sur-Yvette F-9111 France Strategy and Innovation Technology Innovation Schneider Electric Industries 37 Quai Paul Louis Merlin 38050 Grenoble cedex France

As any safety-related system, medium voltage protection relays have to comply with a Safety Integrated Level (SIL), as defined by the IEC 61508 standard. The safety-function of the software part of protection relays is first to detect any faults within the supervised power network, then ask the tripping of the circuit breakers in order to isolate the faulty portion of the network. However, it is required that detection and isolation of faults must occur within a given time, as specified by the IEC 60255 standard. Schneider Electric currently achieves the demonstration that a protection relay is performing its safetyfunction within such temporal constraints at the price of a costly phase of tests. The OASIS approach is a complete tool-chain to build safety-critical deterministic real-time systems, which enables the demonstration of the system timeliness. In this paper, we show how we apply the OASIS approach to build a deterministic protection relay system. We designed a software platform called OASISepam, based on an existing product from Schneider Electric, namely the Sepam 10. We show a preliminary evaluation of our implementation over a STR710 ARM-based board that runs the OASIS kernel. Notably, we show that the observed worst-case end-to-end detection time of OASISepam fulfils the specified constraint expressed in the design phase and translated in the OASIS programming model. Consequently, the temporal behaviour of protection relays is mastered, thus reducing application development costs and allowing the optimization of selectivity. ©2010 ieee.

关键词： real time systems

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