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检索条件"任意字段=IEEE Symposium on Real-Time and Embedded Technology and Applications"

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Hellfire: A design framework for critical embedded systems' applications

Hellfire: A design framework for critical embedded systems' ...

引用

ieee International symposium on Quality Electronic Design

作者： Alexandra Aguiar Sérgio J. Filho Felipe G. Magalhães Thiago D. Casagrande Fabiano Hessel Faculty of Informatics PUCRS Porto Alegre Brazil

ISBN: (纸本)9781424464548

Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded system's constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.

关键词： embedded system Space exploration Hardware Energy consumption real time systems Aerospace electronics Vehicle dynamics Analytical models Timing time to market

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A System-on-a-Chip Platform for Mixed-Criticality applications

A System-on-a-Chip Platform for Mixed-Criticality Applicatio...

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International symposium on Object-Oriented real-time Distributed Computing

作者： Armin Wasicek Christian El-Salloum Hermann Kopetz Institute for Computer Engineering Vienna University of Technology Vienna Austria

High-integrity systems are deployed in order to realize safety-critical applications. To meet the rigorous requirements in this domain, these systems require a sophisticated approach to design, verification, and certification. Not only safety consideration shave an impact on a product's overall dependability, but also security has to be taken into account. In this paper we analyze the time-Triggered System-on-Chip (TTSoC) architecture, which is a novel architecture for Multi-Processor System-on-Chip (MPSoC) devices, regarding its security properties. We discuss essential compliance criteria to the Multiple Independent Layers of Security (MILS) architecture, which is a industry-ready architecture for embedded high-integrity systems. We found that both architectures share intrinsic properties and we are able to show that the TTSoC architecture implements the core requirements of a MILS Separation Kernel and thus realizes its elementary security policies by design.

关键词： System-on-a-chip Application software Operating systems Power system security Virtual machine monitors Distributed computing Kernel Heart Hardware Protection

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A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

A Reconfigurable Network-on-Chip Architecture for Optimal Mu...

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16th IFIP WG 10 5 ieee International Conference on Very Large Scale Integration (VLSI-SoC 2008)

作者： Rana, Vincenzo Atienza, David Santambrogio, Marco Domenico Sciuto, Donatella De Micheli, Giovanni Politecn Milan DEI Via Ponzio 34-5 I-20133 Milan Italy Ecole Polytech Fed Lausanne EPFL Embedded Syst Lab (ESL) IEL STI CH-1015 Lausanne Switzerland Univ Complutense Madrid Dept Arquitectura Computadores Automat DACYA E-28040 Madrid Spain Ecole Polytech Fed Lausanne Integrated Syst Lab ISIM IC CH-1015 Lausanne Switzerland

ISBN: (纸本)9783642122668

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systemson-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive No Cs in industrial So Cs. In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic No Cs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs;thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in So Cs with many possible sets of running applications.

关键词： Networks on Chips Systems on Chips Topology Reconfiguration Express Lines Dynamic Reconfiguration FPGA

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Energy analysis of embedded software based on a cycle-accurate processor power model

Energy analysis of embedded software based on a cycle-accura...

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ieee symposium on Industrial Electronics & applications (ISIEA)

作者： Heiko Hübert Benno Stabernack Image Processing Department Heinrich Hertz Institute Berlin Berlin Germany

The design of embedded systems is often subject to strict requirements concerning various aspects, including real-time performance, power consumption and die area. For mobile devices especially, power consumption is often the most important issue. In order to meet these requirements an adequate system architecture needs to be designed and the embedded software needs to be optimized. For complex applications, this optimization can be fairly difficult and requires an in-depth analysis to reveal the most energy demanding parts of the software. In this paper, we describe a method and its implementation for cycle-accurate software analysis on the function-level, which is based on a RISC processor power model. This analysis method has been used during the implementation of a video coding application in order to show its applicability.

关键词： Power demand Decoding Energy consumption Registers Software Analytical models Power measurement

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realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix

Realization of efficient and low-power parallel face-detecti...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Takeshi Kumaki Yuta Imai Hirokazu Hiramoto Tetsushi Koide Hans Jürgen Mattausch Research Institute of Nanodevices and Bio Systems RNBS Hiroshima University Higashihiroshima Japan

This paper presents an efficient and low-power-consumption parallel face-detection technology based on Haar-like features and implemented with a massive-parallel memory-embedded SIMD matrix. The massive-parallel memory-embedded SIMD matrix architecture has up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For experimented verification of this matrix processing architecture, this parallel Haar-like-feature based face-detection technique has been implemented on an evaluation board and tested in practice. Evaluation results show that a total processing time of about 313 ms at 162 MHz clock frequency and 150 mW power dissipation can be realized. Thus, the reported parallel-face detection method with the massive-parallel memory-embedded SIMD matrix is a practical technology and is a promising solution for real-time mobile multimedia applications.

关键词： Face detection Clocks Frequency Power dissipation CMOS technology Hardware Arithmetic Energy consumption Memory architecture Testing

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Modeling of real-time System Designs for Parametric Analysis

Modeling of Real-Time System Designs for Parametric Analysis

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ieee International Conference on embedded and real-time Computing Systems and applications (RTCSA)

作者： Chaiwat Sathawornwichit Toshiaki Aoki Takuya Katayama School of Information Science Japan Advanced Institute of Science and Technology Ishikawa Japan

In designing real time software, system designers need to find out the time budget to allocate to each action of real time tasks so that the tasks can meet their deadlines. Our solution to this problem involves representing the execution time of the actions as parameters, then analyzing the collaborative behavior of those real time tasks. This paper proposes parametric timed models of real time tasks whose executions are controlled by a scheduler. We develop an algorithm to synthesize a coherent model which represents the possible behavior from a set of real time tasks by exhaustively searching their reachable states. A set of linear inequalities are then derived on the fly from the synthesized model as the condition of parameters for schedulability. By solving the inequalities using a constraint solver, we can obtain desirable values of the parameters. In addition, we have implemented the algorithm in a tool and conducted some experiments to show the effectiveness of our approach.

关键词： Automata Analytical models Software Computational modeling Processor scheduling Concrete Algorithm design and analysis

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Wave field synthesis for next generation videoconferencing

Wave field synthesis for next generation videoconferencing

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4th International symposium on Communications, Control, and Signal Processing, ISCCSP-2010

作者： Lopez, Jose J. Cobos, Maximo Pueo, Basilio Aguilera, Emanuel Institute of Telecommunications and Multimedia Applications Universidad Politecnica de Valencia 46022 Valencia Spain Spain

ISBN: (纸本)9781424462858

Videoconference systems have been around the market for a long time. Their aim is to provide a way of carrying out meetings without the need for having physical presence of the participants. However, the sense of realism achieved by these systems is usually far away from the one expected by the people involved in the communication. This paper presents different advances related with the introduction of Wave-Field Synthesis (WFS) to high-realism 3D videoconference systems. WFS provides an acoustic window that, combined with stereo video screens, generates a very realistic sound field. This paper presents the technologies employed towards the development of real prototypes of these new systems. A multiexcited Distributed Mode Loudspeaker (DML) in the form of Multiactuator Panel (MAP) has been used as an alternative technology to traditional cone loudspeakers. Because of its low visual profile and the fact that the vibration is low enough to be imperceptible to the human eye;they can be integrated into a room interior and simultaneously used as projection screens. ©2010 ieee.

关键词： Loudspeakers

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Low delay Distributed Video Coding using data hiding

Low delay Distributed Video Coding using data hiding

引用

作者： Vijayanagar, Krishna Rao Dan, Bowen Kim, Joohee Illinois Institute of Technology Department of Electrical and Computer Engineering Chicago IL 60616 United States

ISBN: (纸本)9781424471348

Distributed Video Coding (DVC) is a popular topic in the research community and the past years have seen several different implementations. DVC has been proposed as a solution for applications that have limited battery resources and low hardware complexity, thus necessitating a low complexity encoder. An ideal application would be in remote surveillance/monitoring or live video conferencing. However, current solutions use iteratively decodable channel codes like LDPCA or Turbo codes that have large latencies. In order to make real-time communication possible. The proposed architecture makes efficient use of Skip blocks to reduce the bitrate, eliminates the iterative decoding nature of the Wyner-Ziv (WZ) channel and uses a simple data-hiding based compression algorithm. This drastically cuts down on the time complexity of the decoding procedure while still maintaining an rate-distortion performance better than that of H.264/AVC Intra coding and other current DVC solutions. © 2010 ieee.

关键词： Video conferencing

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An embedded system and RFTD solution for transport related issues

An embedded system and RFTD solution for transport related i...

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2nd International Conference on Computer and Automation Engineering, ICCAE 2010

作者： Srinivasan, S. Ranganathan, H. Vani, S. Department of E.C.E. P.B. College of Engineering Chennai India Department of E.C.E. Sakthi Mariamman Engg. College Chennai India

ISBN: (纸本)9781424455850

time and efficiency are matter of priority now. RFTD (Radio Frequency Tdentification) emerges as one of the converging technologies. While transportation plays an important role in urbanization, RFTD is now key catalyst in signifying the merit of it. RFTD plays major role in auto TD applications like RFTD contact less smart cards used by bus riders, in Super market, Textiles and logistics chain management. This paper aims to understand the benefits of RFTD technology in other countries and to identify possibilities extending it to Tndian market. The Global System for Mobile Communications (GSM) has been a great success in providing both voice and low speed data services. The Enhanced Circuit Switched Data on GSM (ECSD) is one of the major evolutionary steps to serve real time high speed data services. Population explosion is the source of so many issues, one among them is transport. Tn this paper, we propose a novel method to tackle traffic related issues. applications such as accident alert, toll gate control, parking slot management, traffic rule violation control are explained in this paper. ©2010 ieee.

关键词： Global system for mobile communications

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Energy-Efficient Static Priority and Speed Assignment for real-time Tasks with Non-deterministic Release times

Energy-Efficient Static Priority and Speed Assignment for Re...

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ieee International Conference on embedded and real-time Computing Systems and applications (RTCSA)

作者： Simon Perathoner Lothar Thiele Jian-Jia Chen Computer Engineering and Networks Laboratory (TIK) Swiss Federal Institute of Technology Zurich Switzerland Institute of Process Control and Robotics (IPR) Karlsruhe Institute of Technology Karlsruhe Germany

Dynamic Voltage Scaling (DVS) has been widely used for decreasing the dynamic power dissipation of processors. For real-time systems, DVS techniques have been developed that permit to meet the timing constraints of multiple real-time tasks and at the same time reduce the overall dynamic energy consumption. Known methods for static priority DVS scheduling are, however, either restricted to simple periodic/sporadic task release patterns or presume full a priori knowledge of task release times. Moreover, none of the present approaches considers the optimization of task priorities for reducing the energy consumption. In this paper we explore how to determine the static priorities and individual execution speeds (supply voltages) of multiple tasks with non-deterministic release times bounded by arrival curves such that the energy consumption is reduced and the real-time constraints are met. The result are different heuristics for the design of DVS-based real-time systems with static priorities. We show that the proposed methodology leads to energy-efficient system designs and demonstrate the applicability of the approach by means of experiments.

关键词： Voltage control Energy consumption real time systems Processor scheduling Program processors Jitter Algorithm design and analysis

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