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56th ieee International symposium on Circuits and Systems (ISCAS)

作者： Ramadurgam, Srikanth Perera, Darshika G. Univ Colorado Colorado Springs Dept Elect & Comp Engn Colorado Springs CO 80918 USA

ISBN: (纸本)9781665451093

With the proliferation of embedded computing, many machine learning (ML) applications have found their way into embedded devices. The SVM classifier is deemed suitable for real-world ML applications, which often comprise large-scale multi-dimensional data. In this paper, we introduce an FPGAbased systolic array architecture to support and accelerate SVM classifier on resource-constrained embedded devices. We also introduce a unique system-level architecture to further enhance speedup and to facilitate real-time processing. Our systolic array achieves a maximum speedup of 107x compared to its software counterparts, and a maximum classification accuracy of 98.5%.

关键词： Systolic array architectures FPGAs embedded hardware machine learning support vector machines

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On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space applications 27

On-Chip Cross-Layer Infrastructure to Leverage System Reliab...

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27th International symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)

作者： Vargas, Fabian Luis IHP Leibniz Inst High Performance Microelect Frankfurt Germany

ISBN: (纸本)9798350359343

This tutorial summarizes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging and tracking in-field real-time circuit speed performance degradation during IC lifetime. Furthermore, after manufacturing process, on-chip sensors can also be used to assess silicon for device screening. Ultimately, this infrastructure allows predicting inflight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in realtime operating system ( RTOS) is further introduced. embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std. Currently, this on-chip infrastructure is being implemented by IHP in different versions of a RISC-V processor. Such design is based on a CMOS 130nm rad-hard technology also developed at IHP.

关键词： On-chip sensor in-field monitoring cross-layer resilience on-chip analytics Silicon lifecycle management (SLM)

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A vision-based solution for water level monitoring in flash floods scenario 19

A vision-based solution for water level monitoring in flash ...

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19th ieee Sensors applications symposium (SAS)

作者： Ando, Bruno Castorina, Salvatore Graziani, Salvatore Univ Catania Dipartimento Ingn Elettr Elettron & Informat DIEE Catania Italy

ISBN: (纸本)9798350369267;9798350369250

Flash floods represent a serious problem, especially in urban areas, due to the consequences of sediment transport and other phenomena affecting security and life quality of citizens. The availability of low-cost solutions for the real-time monitoring of such phenomena, with particular regards to the water level in urban areas, is of main interest for the realization of early warning systems aimed to predict and handle hazardous events. In this paper a water level monitoring system, based on a low-cost vision system and a dedicated signal processing implemented on an embedded hardware platform, is presented. Main advantage of the proposed approach resides in the adopted sensing methodology, which besides being low-cost, allows for a robust estimation of the water level, without the need for active (powered) ground devices. A proof-of-concept aimed prototype has been realized and its performances have been assessed by means of a dedicated experimental survey. Obtained results highlight high sensitivity and specificity in the water level recognition, with an accuracy close to 100% over the whole explored detection range.

关键词： flash floods water level measurement image processing urban monitoring embedded architecture low-cost

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Jumpstart: Fast Critical Service Resumption for a Partitioning Hypervisor in embedded Systems 28

Jumpstart: Fast Critical Service Resumption for a Partitioni...

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28th ieee real-time and embedded technology and applications symposium (RTAS)

作者： Golchin, Ahmad West, Richard Boston Univ Boston MA 02215 USA

ISBN: (纸本)9781665499989

Complex embedded systems are now supporting the co-existence of multiple OSes to manage services once assigned to separate embedded microcontrollers. Automotive systems, for example, now use multiple OSes to consolidate electronic control unit (ECU) functions on a centralized embedded computing platform. Such platforms have the complexity of an industrial embedded PC, with multiple cores and hardware virtualization capabilities. This enables a partitioning hypervisor to spatially and temporally share the physical machine with separate guest OSes, which manage services of different criticality levels. However, PC-class hardware incurs a large latency to bootstrap an OS and associated application-level services. A firmware BIOS performs a power-on-self-test, and then loads OS images into memory from a bootable storage device. This latency is unacceptable in time-critical embedded systems, where important services must be operational within milliseconds of starting the system. In this paper, we present Jumpstart, a PC-class power management approach that minimizes the wakeup delay of a partitioning hypervisor for use in embedded systems. We show how Jumpstart resumes critical OS services and tasks from a low power suspended state in approximately 600 milliseconds, and reduces full system startup delay by a factor of 23. Additionally, Jumpstart consumes minimal power compared to approaches requiring a system boot from a previously powered-off state. By comparison, an alternative firmware-optimized bootloader, called Slim, reduces boot latency by a factor of 1.8.

关键词： partitioning hypervisors power management ACPI real-time operating systems

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BiDSRS plus : Resource Efficient Reconfigurable real time Bidirectional Super Resolution System for FPGAs

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ieee JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2025年第1期15卷 120-132页

作者： Al Amin, Rashed Obermaisser, Roman Univ Siegen Inst Embedded Syst D-57076 Siegen Germany

Super-resolution (SR) systems represent a rapidly advancing area within Information and Communication technology (ICT) due to their significant applications in computer vision and visual communication. Integrating SR systems with Deep Neural Networks (DNNs) is a widely adopted method for leveraging faster and improved image reconstruction. However, the real-time computational demands, extensive energy overhead and the huge memory footprints associated with DNN-based SR systems limit their throughput and scalability. Field-programmable gate arrays (FPGAs) present a viable and promising solution for exploring the structure and architecture of SR systems due to their reconfigurable nature and parallel computing capabilities. The existing FPGA-based solutions can effectively reduce the computational latency in SR systems, they often result in higher resource and energy consumption. Besides, the traditional SR techniques generally focus on either upscaling or downscaling images or videos without offering any scaling reconfigurability. To address these limitations, this paper introduces BiDSRS+, a novel FPGA based resource-efficient and reconfigurable real-time SR system using modified bicubic interpolation method. In addition, BiDSRS+ supports both upscaling and downscaling of images and videos, enhancing its versatility. Evaluations conducted on the Xilinx ZCU 102 FPGA board reveal substantial resource savings, with reductions of 44x LUT, 31x BRAM, and 35x DSP utilization compared to state-of-the-art DNN-based SR systems, albeit with a trade-off in throughput of 0.5x. Furthermore, when compared to leading algorithm-based SR systems, BiDSRS+ achieves reductions of 5.8x LUT, 1.75x BRAM, and 2.3x Power consumption, without compromising the throughput. Due to its high resource efficiency and reconfigurability with a throughput of 4K@60 FPS, BiDSRS+ offers significant advantages in promoting sustainable and energy-efficient green video communication.

关键词： Bicubic interpolation FPGAs reconfigurable reconfigurable super-resolution super-resolution super-resolution

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SBIs: Application Access to Safe, Baremetal Interrupt Latencies 28

SBIs: Application Access to Safe, Baremetal Interrupt Latenc...

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28th ieee real-time and embedded technology and applications symposium (RTAS)

作者： Pan, Runyu Parmer, Gabriel Shandong Univ Sch Comp Sci & Technol Jinan Peoples R China George Washington Univ Washington DC USA

ISBN: (纸本)9781665499989

The continued increase in Cyber-Physical System (CPS) complexity and tightening of Size, Weight and Power (SWaP) constraints are driving the need for consolidation of software tasks onto fewer microcontrollers. Many embedded systems, prominently including those in the Internet-of-Things (IoT), use software packages from multiple untrusted sources, while their network interfaces expose new attack surfaces that are not present in traditional off-line devices. Increased consolidation with untrusted code of various assurance levels complicates system design, and requires increased spatial and temporal isolation between the applications. Current microcontroller protection domain designs are limited by their long interrupt latencies to isolated applications, forcing the system designers to place timing-sensitive application code into the kernel interrupt handlers, trading spatial isolation for tightly-bounded temporal predictability. SBI (Secure Baremetal Interrupt) enables zero-software-cost delivery of interrupts to protection domains in a secure manner that maintains isolation. We demonstrate an implementation of SBI using the new hardware-accelerated interrupt delivery features on TrustZone-M-enabled microcontrollers. This implementation reduces interrupt latencies by up to 95%, while maintaining strong spatial and temporal isolation. We believe SBI could significantly enable future real-time systems that require both isolation and high responsiveness.

关键词： Codes embedded systems Microcontrollers Software packages real-time systems Hardware Network interfaces

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Work in Progress: Emerging from Shadows: Optimal Hidden Actuator Attack to Cyber-Physical Systems 30

Work in Progress: Emerging from Shadows: Optimal Hidden Actu...

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30th ieee real-time and embedded technology and applications symposium, RTAS 2024

作者： Hamid Miji, Md Kausar Liu, Mengyu Akowuah, Francis E Kong, Fanxin The South Dakota School of Mines and Technology Department of Electrical Engineering and Computer Science Rapid CitySD United States University of Notre Dame Department of Computer Science and Engineering South BendIN United States

ISBN: (纸本)9798350358414

Industries are embracing information technology and constructing more robust machines known as Cyber-Physical Systems(CPS) to automate processes. CPSs are envisioned to be pervasive, coordinating, and integrating computation, sensing, actuation, and physical processes. CPSs have various applications in life-critical scenarios, where their performance and reliability can have direct impacts on human safety and well-being. However, CPSs are vulnerable to malicious attacks, and researchers have developed detectors to identify such attacks in different contexts. Surprisingly, little work has been done to detect attacks on the actuators of CPS. Furthermore, actuators face a high risk of optimal hidden attacks designed by powerful attackers, which can push them into an unsafe state without detection. To the best of our knowledge, no such attacks on actuators have been developed yet. In this paper, we design an optimal hidden attack for actuators and evaluate its effectiveness. First, we develop a mathematical model for actuators and then create a linear program for convex optimization. Second, we solve the optimization problem and simulate the optimal attack. © 2024 ieee.

关键词： Cyber Physical System

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SNN-ANN Hybrid Networks for embedded Multimodal Monocular Depth Estimation

SNN-ANN Hybrid Networks for Embedded Multimodal Monocular De...

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ieee-Computer-Society Annual symposium on VLSI (ISVLSI)

作者： Tumpa, Sadia Anjum Devulapally, Anusha Brehove, Matthew Kyubwa, Espoir Narayanan, Vijaykrishnan Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA ChromoLogic LLC Monrovia CA USA

ISBN: (纸本)9798350354119

Monocular depth estimation is a crucial task in many embedded vision systems with numerous applications in autonomous driving, robotics and augmented reality. Traditional methods often rely only on frame-based approaches, which struggle in dynamic scenes due to their limitations, while event-based cameras offer complementary high temporal resolution, though they lack spatial resolution and context. We propose a novel embedded multimodal monocular depth estimation framework using a hybrid spiking neural network (SNN) and artificial neural network (ANN) architecture. This framework leverages a custom accelerator, TransPIM for efficient transformer deployment, enabling real-time depth estimation on embedded systems. Our approach leverages the advantages of both frame-based and event-based cameras, where SNN extracts low-level features and generates sparse representations from events, which are then fed into an ANN with frame-based input for estimating depth. The SNN-ANN hybrid architecture allows for efficient processing of both RGB and event data showing competitive performance across different accuracy metrics in depth estimation with standard benchmark MVSEC and DENSE dataset. To make it accessible to embedded system we deploy it on TransPIM enabling 9x speedup and 183x lower energy consumption compared to standard GPUs opening up new possibilities for various embedded system applications.

关键词： Monocular Depth Estimation Hybrid Network Neuromorphic Computing TransPIM Neuromorphic Sensor

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Software Implementation of real-time EMD-Based Algorithm in embedded Microprocessors for Wearable Devices

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ieee TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2024年 73卷 1页

作者： Wang, Yung-Hung Liang, Sheng-Fu Kuo, Terry B. J. Lin, Yu-Chuan Natl Cent Univ Dept Mech Engn Taoyuan 32001 Taiwan Natl Cheng Kung Univ NCKU Dept Comp Sci & Informat Engn Tainan 701 Taiwan Natl Cheng Kung Univ NCKU Inst Med Informat Tainan 701 Taiwan Natl Yang Ming Chiao Tung Univ Inst Brain Sci Taipei 11221 Taiwan

Empirical mode decomposition (EMD) is a nonlinear, data-dependent method that decomposes a nonstationary signal into a few oscillation modes, which are referred to as intrinsic mode functions (IMFs). However, EMD often suffers from mode-mixing phenomena. Therefore, many disturbance-assisted EMD (DA-EMD) algorithms, such as ensemble EMD (EEMD) and uniform phase EMD (UPEMD), have been developed to resolve this problem. DA-EMD algorithms are powerful signal-processing tools with widespread use in numerous applications. In particular, many emerging industrial or biomedical applications require measuring features by the decomposition of a signal using DA-EMD algorithms in an online, real-time embedded microprocessor (MCU) of a wearable or standalone device. However, due to the high computational and memory costs of DA-EMD algorithms, it is difficult to implement a DA-EMD algorithm using a pure software approach in a resource-limited MCU. Moreover, the quality of the IMFs must be maintained. Computation latency and power consumption must be minimized as well. In this article, we combine fast EMD and the recently developed low-memory EMD (LMEMD) implementation to significantly reduce the run time and memory to meet the real-time constraints. We also develop the adaptive phase number UPEMD to further reduce the run time of UPEMD. In addition, we develop a theory to estimate the relationship between data latency and boundary error so that we can determine the required data latency within the accepted boundary error. Different DA-EMD algorithms are realized in a wearable system to extract clean electrocardiogram (ECG) signals and ECG-derived respiration (EDR) for demonstration. The performances of different DA-EMD algorithms are also compared. The proposed software approach has the advantage of being able to be implemented on various existing embedded platforms as an available and practical signal decomposition solution for edge computing.

关键词： Computational complexity electrocardiogram (ECG) empirical mode decomposition (EMD) memory cost microcontroller real-time wearable device Computational complexity electrocardiogram (ECG) empirical mode decomposition (EMD) memory cost microcontroller real-time wearable device

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Implementation and Evaluation of SiPM-Based Photon Counting Receiver for IoT applications

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ieee INTERNET OF THINGS JOURNAL 2024年第11期11卷 20287-20299页

作者： Li, Yangchun Chitnis, Danial Univ Edinburgh Inst Integrated Micro & Nano Syst Sch Engn Edinburgh EH9 3FF Midlothian Scotland

Silicon photomultipliers (SiPMs) are photon-counting detectors with great potential to improve the sensitivity of optical receivers. Recent studies of SiPMs in communication focus on the speed rather than the power consumption of the receiver. The gain bandwidth product (GBP) of the amplifiers in these post-SiPM readout circuits is significantly higher than the target data rate. Additionally, the SiPM experiments for optical communication are performed using an offline method which uses instruments, including oscilloscopes and personal computers, to process chunks of the transmitted data. In this work, we have developed an embedded real-time field-programmable gate array (FPGA)-based system to evaluate a commercially available 1 mm-sq SiPM. The implemented real-time system achieves data rates from 10 kb/s to 1 Mb/s with a bit error rate (BER) below 1E-3 approaching the Poisson limit. Results showed that reducing either the dark count rate or increasing the data rate leads to lower dark counts per bit time, hence less power penalty to maintain a probability of error (PE) of 1E-3. The numerically simulated results indicated that to maintain the Poisson limit, the minimum GBP of the amplifier in the post-SiPM readout circuit is 120 MHz based on the proposed setup within the tested data rates. This GBP limitation is determined by the noise floor of the read-out circuit. The analysis of the minimum GBP and electrical power consumption of the receiver in photon counting and BER enables the potential future adoption of this receiver technology when high-optical sensitivity is required, such as visible light communications (VLCs) for low-data rate Internet of Things (IoT) applications.

关键词： Photonics Optical receivers Internet of Things real-time systems Field programmable gate arrays Single-photon avalanche diodes Bit error rate Bit error rate (BER) Internet of Things (IoT) optical communication photon counting real-time systems silicon photomultipliers (SiPMs)

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