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Anomaly Detection in Battery Charging Systems: A Deep Sequence Model Approach 21

Anomaly Detection in Battery Charging Systems: A Deep Sequen...

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21st ieee International symposium on Parallel and Distributed Processing with applications, 13th ieee International Conference on Big Data and Cloud Computing, 16th ieee International Conference on Social Computing and Networking and 13th International Conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Zheng, Li Ding, Donghui Li, Zhao Gao, Jun Xiao, Jie Chen, Hongyang Dustdar, Schahram Zhang, Ji The Key Laboratory of High Confidence Software Technologies Ministry of Education China Peking University School of Computer Science Beijing China Hangzhou Yugu Technology Hangzhou China East China Normal University Shanghai China Zhejiang Lab Hangzhou China Technical University of Vienna Austria University of Southern Queensland Toowoomba Australia

ISBN: (纸本)9798350329223

While the popularity of electric vehicles brings great convenience to our lives, battery charging also leads to an increase in accidents, resulting in personal injuries and economic losses. The methods currently embedded in charging hardware mainly focus on the short-term state of the battery and fail to leverage historical information effectively. The development of the Industrial Internet of Things (IIoT) enables data collection from sensors on industrial devices, which can be analyzed using deep learning methods to support sophisticated analysis. This paper proposes an intelligent and secure battery charging system in the IIoT that establishes an interaction between battery charging devices and cloud-based algorithms. A novel anomaly detection method is introduced to deal with anomalous charging sequences by making good use of historical data. We evaluate our system using real-life data from 4,940 batteries in electric vehicles, and our experiments achieve satisfactory results in detecting anomalies in battery charging. © 2023 ieee.

关键词： Charging (batteries)

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embedded Hardware Implementation of Noise Gate on STM32 Processor Using MATLAB/Simulink

Embedded Hardware Implementation of Noise Gate on STM32 Proc...

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2024 International Conference on Photonics Solutions, ICPS 2024

作者： Jongsataporn, Thitaphan Chivapreecha, Sorawat Department of Industrial Physic and Medical Instrumentation King Mongkut's University of Technology North Bangkok 1518 Pracharat 1 Road WongsawangBangsue Bangkok10800 Thailand School of Engineering King Mongkut's Institute of Technology Ladkrabang 1 Chalong Krung Lat Krabang Bangkok10520 Thailand

ISBN: (数字)9781510688308

ISBN: (纸本)9781510688292

This paper presents a model-based approach for developing a digital signal processing (DSP) system, specifically focusing on a Noise Gate application, using MATLAB/Simulink, and deploying it on the STM32F769I-Discovery board. The study thoroughly examines the advantages of model-based hardware implementation, particularly in facilitating rapid prototyping for real-time applications in educational contexts. The STM32F769I is powered by a high-performance Arm® Cortex®-M7 core, which can execute DSP instructions efficiently. Its ample memory and built-in debugging tools enhance its suitability for complex signal processing tasks. The implementation leverages MATLAB/Simulink and its robust compatibility with the STM32 hardware, allowing for seamless software and hardware component integration. The powerful model-based development features streamline the transition from simulation to physical hardware, reducing development time and enhancing reliability. The Noise Gate application is designed to control audio signals effectively, eliminating unwanted background noise through user-defined parameters such as threshold, attack time, and release time, which optimize performance based on specific audio environments. Additionally, the design applies a first-order IIR low-pass as a smoothing filter, which dynamically adjusts the gain according to the characteristics of the incoming audio signal. This ensures gradual opening and closing of the gate, resulting in smoother audio transitions. The results demonstrate significant noise suppression and overall audio quality enhancement, highlighting the practicality of employing model-based design methodologies for DSP applications. Furthermore, the insights gained from this study contribute to efficient hardware prototype development and offer implications for future projects in the field of digital signal processing. © 2025 SPIE.

关键词： Program debugging

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Optimizing Video Compression and Transmission for real-time applications

Optimizing Video Compression and Transmission for Real-Time ...

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2023 ieee Region 10 symposium, TENSYMP 2023

作者： Sharma, Sugandha Jindal, Harsh Jain, Amit Singh, Shatvik Binner, Pritpal Singh Chandgarh University Department of Computer Science & Engineering Mohali India University Institute of Computing Chandgarh University Mohali India

ISBN: (纸本)9781665482585

Customers' expectations for content have significantly increased in recent times, leading to a perpetual sense of dissatisfaction. They now demand fast loading times and uninterrupted video playback when using on-demand video platforms like YouTube and Netflix. Despite various CNN-based methods proposed to improve compressed video quality, the existing VVC and transmission protocols are struggling to meet the demands of this expanding market of content consumers. To tackle this problem, we present the latest video coding standard, H.266/VVC, which has been developed by Team JVET. H.266 employs a quad-tree with a layered multitype tree structure, although this approach increases the computational requirements for future video coding advancements. However, it is essential for enhancing the acceptance and utilization of video coding technology. Furthermore, we introduce the 'HESP' protocol for video coding-streaming, which enables the delivery of streaming services with extremely low latency and significantly reduced streaming bandwidth on a large scale. © 2023 ieee.

关键词： Efficiency

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Study on the Characteristics of 3.5kV Buried FS Layer Pulse Thyristor 3

Study on the Characteristics of 3.5kV Buried FS Layer Pulse ...

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3rd International symposium on Semiconductor and Electronic technology, ISSET 2024

作者： Zhang, Chao Wang, Cailin Liang, Xiaogang Yang, Wuhua Bai, Tianqi Dong, Shuangfu Xi'an University of Technology Department of Electronic Engineering Xi'an China Fuxin Tianqi Electronics Co. Ltd. Fuxin China

ISBN: (纸本)9798350390285

Pulse thyristors have found wide applications in the field of pulsed power technology due to their high peak current and high voltage withstand capabilities. However, traditional round pulse thyristors are constrained by process conditions. During turn-on, the relatively slow two-dimensional expansion speed of carriers can lead to local overheating and subsequent device failure under high di/dt conditions due to current concentration. Additionally, specific application scenarios require pulse thyristors to possess a certain level of reverse voltage withstand capability. This paper proposes a square pulse thyristor with an embedded FS layer and conducts simulation studies on key parameters affecting device characteristics. The results indicate that increasing the cathode width WN+ and cell width Wcell is beneficial for reducing the on-state voltage drop, and increasing WN+ is conducive to enhancing the peak current. However, excessively large WN+ and Wcell can result in uneven current distribution beneath the N+ cathode region. Reducing the subsurface concentration NN+-Pbase in the P-base region aids in decreasing the on-state voltage drop, but excessively low NN+-Pbase can adversely affect the device's forward voltage withstand capability. The concentration of the FS layer (NFS), the thickness of the N2-base region (dN2-), and NN+-Pbase all positively correlate with the device's turn-on delay time. The minority carrier lifetime influences the device's blocking characteristics, conduction characteristics, and pulsed discharge characteristics, with a positive correlation observed. In practical processes, gettering techniques can be employed to maximize the minority carrier lifetime, thereby ensuring optimal device characteristics. © 2024 ieee.

关键词： Pulsed power technology

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OpTIFlow - An optimized end-to-end dataflow for accelerating deep learning workloads on heterogeneous SoCs

OpTIFlow - An optimized end-to-end dataflow for accelerating...

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IS and T International symposium on Electronic Imaging: Autonomous Vehicles and Machines, AVM 2023

作者： Jagannathan, Shyam Pothukuchi, Vijay Jesse, Villarreal Desappan, Kumar Mathew, Manu Ravikumar, Rahul Limaye, Aniket Mody, Mihir Swami, Pramod Goswami, Piyali Rodriguez, Carlos Embedded Processors Business Texas Instruments United States Emmanuel Madrigal Marco Herrera United States

A typical edge compute SoC capable of handling deep learning workloads at low power is heterogeneous by design. It hosts multiple compute modules such as real-time IPs for capture and display, hardware accelerators for imaging, computer vision, deep learning, multimedia codecs, GPU for 2D/3D visualization and CPU cores such as ARM and DSP for general compute. Every participating compute module transacts using common resources such as system interconnect, L3/L4/DDR memory systems to seamlessly exchange data between them. A careful orchestration of this dataflow is important to keep every producer-consumer at full utilization without causing any drop in real-time performance. The software stack for such complex workflows can be quite intimidating for customers to bring-up and more often act as an entry barrier for many to even evaluate the device. In this paper we propose techniques developed on TI's latest TDA4V-Mid SoC, targeted for automotive and industrial applications;designed around ease-of-use and device entitlement class of performance out-of-box using community popular open standards such as GStreamer, OpenVx, OpenCV, TFLite-RT, ONNX-RT, Neo-AI-DLR runtimes. © 2023, Society for Imaging Science and technology.

关键词： System-on-chip

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On-Chip Infrastructure for Mission-Mode Monitoring of Aero-Space applications: Towards Silicon Lifecycle Management 31

On-Chip Infrastructure for Mission-Mode Monitoring of Aero-S...

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31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)

作者： Vargas, Fabian Luis IHP Leibniz Inst High Performance Microelect Frankfurt Germany

ISBN: (纸本)9798350375701;9788363578268

This tutorial summarizes the on-chip cross-layer infrastructure such as sensors and monitors under development at IHP Microelectronics. This infrastructure deals with detecting single-event upset (SED) in flip-flops, single-event transient (SET) in combinational logic, monitoring power-bus activity and electronics aging evolution. At a higher level, this infrastructure allows detecting faults that affect the real-time operating system (RTOS) activity in a mixed-criticality environment (i.e., faults that affect the task scheduling process by violating execution deadline, time and space allocated for critical tasks under execution). This infrastructure can be used for on-chip analytics to predict in-flight SED rate. Such solution enables mission-mode monitoring of system operation, which is a critical aspect of silicon lifecycle management (SLlM) framework. Currently, this on-chip infrastructure is being implemented in different versions of a RISC-V processor. Such design is based on the IHP's CMOS 130nm rad-hard technology.

关键词： On-chip sensor in-field monitoring cross-layer resilience on-chip analytics silicon lifecycle management

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Prediction of urban traffic congestion time by BPneural network 21

Prediction of urban traffic congestion time by BPneural netw...

引用

21st International symposium on Distributed Computing and applications for Business Engineering and Science, DCABES 2022

作者： Haoran, Liu Suyan, Zhao Xin, Liu Jie, Li Shandong University of Science and Technology Qingdao266000 China

ISBN: (纸本)9781665454629

This paper studies the time prediction of traffic congestion, through the real-time speed of the car, The free flow speed, the morning and evening peaks, the number of weeks, the average speed of the car in this section are used as independent variables, and the time of traffic congestion is studied as a dependent variable. Through the MATLAB R2014a numerical simulation software for BP neural network operation, the neuron input layer is the real-time speed, free flow speed, morning and evening peak, week number, and average vehicle speed factor of the car after processing. The prediction result is good, which proves that the model is effective and reliable, and can estimate the time of the vehicle passing through the crowded road section. © 2022 ieee.

关键词： Traffic congestion

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Removal of electrocardiographic interference and artifacts from diaphragm electromyography

Removal of electrocardiographic interference and artifacts f...

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2023 ieee International symposium on Medical Measurements and applications, MeMeA 2023

作者： Gronska, Gabriela Peri, Elisabetta Long, Xi Dijk, Johannes P. Van Mischi, Massimo Eindhoven University of Technology Department of Electrical Engineering Eindhoven Netherlands Eindhoven University of Technology Center for Sleep Medicine Kempenhaeghe Heeze Netherlands

ISBN: (纸本)9781665493840

Diaphragmatic electromyography (dEMG) holds the potential to monitor respiration. However, its acquisition is affected by electrocardiographic (ECG) interference and motion artifacts, making its investigation and use in clinical practice still challenging. Singular value decomposition (SVD) methods have been reported in the literature denoising the dEMG. Here a new ratio index criterion is combined with a SVD based algorithm to aid this challenge. The advantage of the proposed approach is in use of the frequency spectrum as a reference to remove unwanted components from the signal. Two synthetic datasets combining EMG with ECG only and with ECG and motion artifacts were tested using a signal-to-noise ratio ranging from -20 to 0dB to assess the performance of the method. The performance was compared with an earlier developed SVD-based algorithm that employed a calibration curve for the selection of unwanted components. Our results show that our new proposed method reached significantly better performance in both time and frequency domains for the majority of presented SNRs in the dataset containing artifacts. Additionally for the same dataset, the method obtained the average median improvement in the SNR of 12 dB and, the average median percentage improvement of 157% in the reconstructed EMG signal. The solution does not need an additional reference for the ECG. Its performance was proven on the data containing not only electrocardiographic disturbance but also motion artifacts, showing promise for further use on the real data. © 2023 ieee.

关键词： Singular value decomposition

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Deep learning Based Glue Line Defect Detection 18

Deep learning Based Glue Line Defect Detection

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18th ieee Conference on Industrial Electronics and applications, ICIEA 2023

作者： Tong, Yingnan Qiu, Jun Lin, Hongye Wang, Yongbin Zhejiang University School of Control Sciences and Engineering Hang Zhou China NingBoTech University School of Information Science and Engineering NingBo China Jiangxi University of Science and Technology School of Electrical Engineering and Automation Ganzhou China

ISBN: (纸本)9798350312201

Most factories use automatic dispensing machines for workpiece sealing, and the processing efficiency is very high. The traditional manual detection is inefficient and costly. Besides, the rate of false detection and missed detection of defect products remains high. In view of this problem, this paper proposes a glue line defect detection model based on Yolov5 and the self-built workpiece defect data set is used for the research. Firstly, some conventional convolution modules in Backbone network are replaced with the corresponding deformable convolution modules to improve the generalization ability of the model. Then in order to improve the feature extraction ability of the model, the coordinate attention module is embedded in the Backbone network. The results show that the mean average precision of the proposed algorithm can reach 95.62%, which is greatly higher than initial Yolov5 algorithm. And the detection rate reaches 28.67 FPS, which can meet the real time detection. © 2023 ieee.

关键词： Convolution

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IO Virtualization for real time Automotive Systems

IO Virtualization for Real Time Automotive Systems

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2022 ieee International Conference on Consumer Electronics, ICCE 2022

作者： Sriramakrishnan, Govindarajan Mody, Mihir Shurtz, Gregory Fuoco, Chuck Chitnis, Kedar Devshatwar, Nikhil Steiss, Don Bergsagel, Jonathan Jones, Jason Y A, Prithvi Shankar Texas Instruments Incorporated Embedded Processor Division Bangalore India Texas Instruments Incorporated Embedded Processor Division Houston United States Texas Instruments Incorporated Embedded Processor Division Dallas United States

ISBN: (纸本)9781665441544

Virtualization is common in enterprise systems to isolate multiple server applications using the same underlying HW. In automotive systems virtualization is fast becoming table stakes to isolate safety applications like ADAS (Advanced Driver Assist System) and infotainment using the same underlying SOC. This presents unique challenges related to peripheral IO virtualization, not seen in enterprise systems, like deterministic latency to external memory ( © 2022 ieee.

关键词： Cameras

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