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A Runtime-Efficient Multi-Object Tracking Approach for Automotive Perception Systems 17

A Runtime-Efficient Multi-Object Tracking Approach for Autom...

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17th ieee International symposium on Applied Computational Intelligence and Informatics, SACI 2023

作者： Lindenmaier, Laszlo Czibere, Balazs Aradi, Szilard Becsi, Tamas Budapest University of Technology and Economics Dept. of Control for Transportation and Vehicle Systems Budapest Hungary

ISBN: (纸本)9798350321104

There is an increasing demand for fully autonomous driving with the spread of advanced driver assistance systems. However, a higher level of automation requires an enhanced environment perception system. The automotive smart sensors detecting the surrounding objects are usually subject to various uncertainties. Objects are sometimes misdetected, false detections may also occur, and the sensor measurements are noisy. Multi-object tracking algorithms aim to compensate for these uncertainties, estimating precisely and continuously the state of surrounding objects. The real-time execution of these algorithms is crucial in automotive applications. This paper presents an improved runtime-efficient local nearest neighbor-based approach. The performance metrics of the proposed method get close to the state-of-the-art algorithms, besides having significantly lower computational complexity. © 2023 ieee.

关键词： Object detection

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Design of embedded Remote Working Condition Monitoring System Based on Wireless Network Bridge 16

Design of Embedded Remote Working Condition Monitoring Syste...

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16th ieee Conference on Industrial Electronics and applications (ICIEA)

作者： Yang, Chunling Lu, Fangyong Zhu, Min Liu, Min Harbin Inst Technol Sch Elect Engn Harbin Peoples R China

ISBN: (纸本)9781665422482

With the development of computer network technology, remote working condition monitoring system is gradually applied to the fields of traffic and road condition, construction site, and oil well site monitoring. The traditional monitoring system can achieve its basic functions to a certain extent, but on the one hand, it does not solve the problem of simultaneous transmission of working condition data and real-time images;on the other hand, the networking is not flexible enough. Based on the embedded development board and wireless bridge communication technology, this paper constructs an embedded remote working condition monitoring system. This system combines the V4L2 (Video for linux2) programming framework provided by Linux, and transplants the collection and sending program of working condition data and image data in the development board. First, the development board collects and packs the data;then, the data is transmitted to the upper monitoring center through the wireless bridge to realize real-time monitoring of the scene and real-time display and alarm of working condition data. This paper designs and implements an embedded remote working condition monitoring system, and builds an experimental platform to verify its feasibility.

关键词： embedded wireless bridge working condition monitoring real-time

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A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design 24

A Sparsity-Aware Autonomous Path Planning Accelerator with A...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Zhang, Yanjun Niu, Xiaoyu Zhang, Yifan Tian, Hongzheng Yu, Bo Liu, Shaoshan Huang, Sitao Beijing Institute of Technology China University of California Irvine United States Shenzhen Institute of Artificial Intelligence and Robotics for Society China

ISBN: (纸本)9798400710773

Path planning is a critical task in autonomous driving systems that is most susceptible to real-time constraints but often demands computationally intensive mathematical solvers, two contradictory goals. This conflict makes the computing of path planning a paramount challenge. At the heart of most path planners is the quadratic programming (QP) solver, which places excessive demands on the CPU in real-world autonomous driving applications. In this paper, we present an FPGA-based acceleration framework for path planning problems. Our approach leverages an operator splitting solver for quadratic programs (OSQP) and employs the preconditioned conjugate gradient (PCG) method for solving linear systems, which are customized to be more hardware-friendly than prior works. Specific memory management and parallel processing were tailored to the matrix pattern, and the incorporation of pipelining was executed to enhance throughput and execution speed. Our FPGA-based implementation achieves state-of-the-art performance against existing works, including an average 1.98× speedup compared with the state-of-the-art QP solver on Intel i7-11800H CPU, 3.90× speedup over an ARM Cortex-A57 embedded CPU, and 12.3× speedup over an NVIDIA RTX 3090 GPU. © 2024 Copyright is held by the owner/author(s).

关键词： Quadratic programming

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Optimizing Convolutional Neural Networks for Plant Disease Detection on ARM-M Microcontrollers

Optimizing Convolutional Neural Networks for Plant Disease D...

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2024 ieee International Conference on Agrosystem Engineering, technology and applications, AGRETA 2024

作者： Nugroho, Hermawan Xan, Chew Jing Siang, Tay Fei Eswaran, Sivaraman University of Nottingham Malaysia Department of Electrical and Electronic Engineering Semenyih Malaysia Swinburne University of Technology Sarawak Campus Faculty of Engineering Computing and Science Sarawak Malaysia Curtin University Malaysia Department of Electrical and Computer Engineering Miri Malaysia

ISBN: (纸本)9798350373660

Rice production in Malaysia is facing significant challenges due to plant diseases and environmental hazards, leading to a decline in the rice self-sufficiency ratio. To address these issues, this study explores the deployment of AI-driven plant disease detection models on ARM-M based microcontrollers, specifically the STM32H747I-DISCO Discovery kit. Utilizing Convolutional Neural Networks (CNNs) for image recognition, we aim to achieve real-time disease monitoring without relying on continuous internet connectivity. Our research evaluates five state-of-the-art models-FD-MobileNet, MobileNet V1, MobileNet V2, ResNet V1, and SqueezeNet V1-focusing on their suitability for resource-constrained environments. The results indicate that FD-MobileN et is the most resource-efficient model with the lowest number of Multiply-Accumulate operations (MACCs) and the shortest inference time, achieving an accuracy rate of 98.44%. However, SqueezeNet, despite having the highest accuracy at 99.22%, faces deployment challenges due to its large model size on the STM32H747I-DISCO board. This work highlights the potential of embedded AI applications in enhancing agricultural resilience and efficiency. © 2024 ieee.

关键词： Convolutional neural networks

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Implementation of a Watchdog timer's Microarchitecture and design for a RISC-V-based SoC using 45nm technology

Implementation of a Watchdog timer's Microarchitecture and d...

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2024 Asian Conference on Intelligent Technologies, ACOIT 2024

作者： Chaithanya, D.J. Kurthukoti, Anoushka Ameet Nandi, Yajnika S. Harshitha, M.S. Parvitha, U. Pavan Athreya, A. Dept. of Electronics and Communication Engineering Vidyavardhaka College of Engineering Mysuru India Dept. of Information Science and Engineering Vidyavardhaka College of Engineering Mysuru India

ISBN: (纸本)9798350374933

WDT in safety-critical embedded systems, such as the one used for airborne application requires that it be highly dependable and take care of operation time-related failures automatically and transparently to ensure high dependability can be achieved with their use. In developing such a WDT, one challenge is taking an existing off-the-shelf capable device, which is typically highly specialized for single-purpose end-doing approaches. This work helps to resolve this challenge by developing a next-generation programmable WDT and using it in various applications. The WDT that will be proposed is a processor-based real-time system where the capabilities and activities in the processor are significantly more common. The effectiveness of the proposed WDT is assessed using simulation results to determine its capability to identify the kind of defects and to take pertinent actions. Test benches have been integrated to create errors in the design and track a system's operation, which is necessary for the WDT to function properly. Verilog HDL, a hardware description language widely used in digital circuit design, is utilized to create WDT. The goal of this work is to provide generalizable WDT that may be used in a variety of contexts, including ones that are safety focused. To ensure that the WDT is operating as intended and that it can be depended upon for handling the process duration during failure, simulation, and test benches are employed. © 2024 ieee.

关键词： Watches

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2023 ieee India Geoscience and Remote Sensing symposium, InGARSS 2023

2023 IEEE India Geoscience and Remote Sensing Symposium, InG...

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3rd ieee India Geoscience and Remote Sensing symposium, InGARSS 2023

ISBN: (纸本)9798350325591

The proceedings contain 119 papers. The topics discussed include: unmasking devastation: near real-time earthquake-induced building damage detection;investigating the viability of detecting rooftop solar photovoltaics via convolutional neural networks using remote sensing images;mapping Maharashtra’s slums using Google Earth engine;microwave NDT for estimating organic textile dye residue on top soil;active learning using multifeature kernel sparse representation classifier for hyperspectral image classification;investigating large vision model training challenges on satellite datasets;TLS, GNSS and TS survey planning for precision agricultural applications;and remote sensing image de-striping using deep convolutional networks.

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Enhancing Traffic Management with embedded Machine Learning for Vehicle Detection

Enhancing Traffic Management with Embedded Machine Learning ...

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2023 International Conference on Microelectronics, ICM 2023

作者： Talip, Mohamad Sofian Abu Razak, Mohd Zulhakimi Ab Mohamad, Mahazani Khairuddin, Anis Salwa Mohd Izam, Tengku Faiz Tengku Mohmed Noor Azizan, Azizul University of Malaya Faculty of Engineering Department of Electrical Engineering Kuala Lumpur50603 Malaysia Institute of Microengineering and Nanoelectronics Universiti Kebangsaan Malaysia Bangi Selangor 43600 Malaysia Universiti Teknologi Malaysia Razak Faculty of Technology and Informatics Advanced Informatics Department Kuala Lumpur54100 Malaysia

ISBN: (纸本)9798350380828

In recent years, vehicle detection has become vital for applications ranging from autonomous driving to traffic control, surveillance, and monitoring. The demand for efficient real-time detection systems has surged, prompting the integration of machine learning algorithms into embedded platforms as a promising approach. This paper focuses on developing a robust and efficient system deployable on the NVIDIA Jetson Nano 2GB Developer Kit. The system harnesses machine learning algorithms tailored for resource-constrained embedded systems to achieve high detection accuracy in realtime. The process encompasses data preparation, preprocessing, feature extraction, and classification. Deep learning models used are You Only Look Once (YOLO) algorithm, YOLOv5n, and YOLOv7-tiny, trained on labeled datasets to classify regions of interest based on unique vehicle attributes. For inference on the Jetson Nano, both are chosen for their real-time capabilities and high object detection accuracy, are employed. To leverage the Jetson Nano's GPU power, NVIDIA's Compute Unified Device Architecture (CUDA) toolkit is installed, enabling parallel computing and deep learning model optimization. Results indicate that YOLOv7-tiny achieves the better precision-confidence at 92.7% and a recall-confidence of 94% compared to YOLOv5n. This study also uses various other evaluation metrics such as accuracy, precision, recall, confusion matrix, and F1 score to measure system performance and examine computational efficiency, to help in the selection of appropriate models for embedded systems. © 2023 ieee.

关键词： embedded systems

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Accuracy Configurable FPGA Implementation of Harris Corner Detection

Accuracy Configurable FPGA Implementation of Harris Corner D...

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ieee-Computer-Society Annual symposium on VLSI (ISVLSI)

作者： Maurya, Shivani Choudhury, Ziaul Purini, Suresh Int Inst Informat Technol Ctr VLSI & Embedded Syst Technol Hyderabad India

ISBN: (数字)9781665466059

ISBN: (纸本)9781665466059

Image processing algorithms with intrinsic robustness to errors can be approximated for significant resource and energy savings while still meeting the end-user requirements. FPGA-based implementations can increase their suitability for real-time high-speed multimedia applications by leveraging Approximate Computing, an independent field that explores methods to reduce computation costs by allowing minor degradation in intermediate computations. With high volume of pixel level computations, corner detection algorithms such as the Harris Corner Detector (HCD), offer wide range of targets for such strategies. In this paper, we propose an hardware implementation of HCD that relies on approximating the intermediate multiplication operations using Dynamic Range Unbiased Multiplier (DRUM). With run-time configurable bit-width control of DRUM instances, the visual quality of outputs is shown to depend on the varying accuracy of the corner response. We explore how the errors due to approximate operations propagate to the corner response and attempt to find a threshold that adapts to this inaccuracy across images. The experimental results for implementations on Virtex-7 and Zynq-7000 FPGA devices show that our approximate architecture can match the performance of other HCD implementations while hardly utilizing any on-board memory and signal processing resources. Synthesis results show that the proposed implementation achieves over 60% increase in maximum frequency compared to the base implementation. Finally, the quality metric analysis facilitates the selection of approximate configuration suited to the needs of an application.

关键词： FPGA Approximate Computing DRUM Image Processing Harris Corner Detector Bluespec Zynq Virtex

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A Systolic Array Architecture for SVM Classifier for Machine Learning on embedded Devices

A Systolic Array Architecture for SVM Classifier for Machine...

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ieee International symposium on Circuits and Systems (ISCAS)

作者： Srikanth Ramadurgam Darshika G. Perera Department of Electrical and Computer Engineering University of Colorado Colorado Springs Colorado Springs USA

With the proliferation of embedded computing, many machine learning (ML) applications have found their way into embedded devices. The SVM classifier is deemed suitable for real-world ML applications, which often comprise large-scale multi-dimensional data. In this paper, we introduce an FPGA-based systolic array architecture to support and accelerate SVM classifier on resource-constrained embedded devices. We also introduce a unique system-level architecture to further enhance speedup and to facilitate real-time processing. Our systolic array achieves a maximum speedup of 107x compared to its software counterparts, and a maximum classification accuracy of 98.5%.

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New Response time Analysis for PWLP on Multiprocessor Mixed-Criticality Systems

New Response Time Analysis for PWLP on Multiprocessor Mixed-...

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International symposium on Industrial embedded Systems

作者： Hanzhi Xu Ruoxian Su Jieyu Jiang Meixuan Zhang Shuai Zhao School of Computer Science and Engineering Sun Yat-sen University China

ISBN: (数字)9798350388633

ISBN: (纸本)9798350388640

The Preemptable Waiting Locking Protocol (PWLP) is a mainstream real-time resource sharing protocol that provides predictable mutually exclusive access to shared resources. However, the analysis of PWLP can only support traditional real-time systems, preventing its application in mixed-criticality systems (MCS), which are commonly found in realistic real-time applications. In addition, existing analyses are either overly-pessimistic or computationally extensive with optimizations required. To address the above issues, this paper presents a new response time analysis of PWLP on multiprocessor MCS, enhancing both the effectiveness and applicability of PWLP on MCS. The proposed analysis provides fine-grained blocking bounds of PWLP and explicitly considers the varied task execution time under MCS, achieving accurate timing bounds without significantly increasing computation cost. Experimental results show that the proposed analysis outperforms existing analysis by improving the resulting system schedulability with much less computation cost.

关键词： Costs Protocols embedded systems Accuracy Computer architecture real-time systems Timing time factors Resource management Optimization

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