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A Systolic Array Architecture for SVM Classifier for Machine Learning on embedded Devices

A Systolic Array Architecture for SVM Classifier for Machine...

引用

ieee International symposium on Circuits and Systems (ISCAS)

作者： Srikanth Ramadurgam Darshika G. Perera Department of Electrical and Computer Engineering University of Colorado Colorado Springs Colorado Springs USA

With the proliferation of embedded computing, many machine learning (ML) applications have found their way into embedded devices. The SVM classifier is deemed suitable for real-world ML applications, which often comprise large-scale multi-dimensional data. In this paper, we introduce an FPGA-based systolic array architecture to support and accelerate SVM classifier on resource-constrained embedded devices. We also introduce a unique system-level architecture to further enhance speedup and to facilitate real-time processing. Our systolic array achieves a maximum speedup of 107x compared to its software counterparts, and a maximum classification accuracy of 98.5%.

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New Response time Analysis for PWLP on Multiprocessor Mixed-Criticality Systems

New Response Time Analysis for PWLP on Multiprocessor Mixed-...

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International symposium on Industrial embedded Systems

作者： Hanzhi Xu Ruoxian Su Jieyu Jiang Meixuan Zhang Shuai Zhao School of Computer Science and Engineering Sun Yat-sen University China

ISBN: (数字)9798350388633

ISBN: (纸本)9798350388640

The Preemptable Waiting Locking Protocol (PWLP) is a mainstream real-time resource sharing protocol that provides predictable mutually exclusive access to shared resources. However, the analysis of PWLP can only support traditional real-time systems, preventing its application in mixed-criticality systems (MCS), which are commonly found in realistic real-time applications. In addition, existing analyses are either overly-pessimistic or computationally extensive with optimizations required. To address the above issues, this paper presents a new response time analysis of PWLP on multiprocessor MCS, enhancing both the effectiveness and applicability of PWLP on MCS. The proposed analysis provides fine-grained blocking bounds of PWLP and explicitly considers the varied task execution time under MCS, achieving accurate timing bounds without significantly increasing computation cost. Experimental results show that the proposed analysis outperforms existing analysis by improving the resulting system schedulability with much less computation cost.

关键词： Costs Protocols embedded systems Accuracy Computer architecture real-time systems Timing time factors Resource management Optimization

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Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA 25

Hardware-in-the-loop simulation of a UAV autonomous landing ...

引用

25th ieee Conference on Signal Processing - Algorithms, Architectures, Arrangements, and applications (ieee SPA)

作者： Szolc, Hubert Kryjak, Tomasz AGH Univ Sci & Technol Dept Automat Control & Robot Comp Vis Lab Embedded Vis Syst Grp Krakow Poland

ISBN: (数字)9788362065424

ISBN: (纸本)9788362065424

This paper presents a system for hardware-in-the-loop (HiL) simulation of unmanned aerial vehicle (UAV) control algorithms implemented on a heterogeneous SoC FPGA computing platforms. The AirSim simulator running on a PC and an Arty Z7 development board with a Zynq SoC chip from AMD Xilinx were used. Communication was carried out via a serial USB link. An application for autonomous landing on a specially marked landing strip was selected as a case study. A landing site detection algorithm was implemented on the Zynq SoC platform. This allowed processing a 1280 x 720 @ 60 fps video stream in real time. Performed tests showed that the system works correctly and there are no delays that could negatively affect the stability of the control. The proposed concept is characterised by relative simplicity and low implementation cost. At the same time, it can be applied to test various types of high-level perception and control algorithms for UAV implemented on embedded platforms. We provide the code developed on GitHub, which includes both Python scripts running on the PC and C code running on Arty Z7.

关键词： Hardware-in-the-loop HiL Unmanned Aerial Vehicle UAV FPGA SoC autonomous landing

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Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security applications 21

Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-...

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21st International System-on-Chip Design Conference, ISOCC 2024

作者： Dinh, Nhat Nguyen Luan Pham, Hoai Duong Le, Vu Trung Hai Vu, Tuan Tran, Van Duy Nakashima, Yasuhiko University of Information Technology - VNUHCM Viet Nam Nara Institute of Science and Technology Nara630-0192 Japan

ISBN: (纸本)9798350377088

Hardware development for CRYSTALS-Kyber is essential to prevent future quantum computer attacks. However, existing CRYSTALS-Kyber hardware often has low performance and lacks the flexibility to support the three operation modes: key generation, encryption, and decryption. To address this issue, we propose the Multi-Mode CRYSTALS-Kyber Accelerator, named Kyberator, which supports all three operation modes with high speed and hardware efficiency. Notably, this paper is the first to analyze the real-time performance at an actual system-on-chip (SoC) level on an embedded FPGA platform, demonstrating that the power-delay product of the Kyberator is 4.9 to 10.1 times greater than that of the most powerful current CPUs. Compared with related works on FPGA, the Kyberator is at least 2.1 times better in terms of area-delay product and offers better flexibility. © 2024 ieee.

关键词： System-on-chip

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Ai Machine Learning: Transformer Models For Enhanced Natural Language Processing - Techniques And applications 12

Ai Machine Learning: Transformer Models For Enhanced Natural...

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12th International Conference on Internet of Everything, Microwave, embedded, Communication and Networks, IEMECON 2024

作者： Pragith, S. Karthik, G.M. Sripriya, T. Rajasekaran, E. Periannasamy, S. Manthandi Aslam, Mohamed Zubair M.A. Department of Computer Science Engineering Vellore Institute of Technology Tamil Nadu Vellore India Vellore Institute of Technology Tamil Nadu Vellore India Department of ECE Jeppiaar Institute of Technology Tamil Nadu Chennai India Department of Science and Humanities V.S.B Engineering College Tamil Nadu Karur India Department of Electronics and Communication Engineering Mallareddy Engineering College for Women Maisammaguda Hyderabad India Department of AI &DS Dhanalakshmi College of Engineering Tamil Nadu Chennai India

ISBN: (纸本)9798350387315

Modern technologies are needed to strengthen network security defenses because of the increase in cyber attacks in recent years. Because deep learning in particular allows for real-time threat identification and thorough performance evaluation, artificial intelligence (AI) has become a powerful tool for improving cybersecurity measures. This study examines how deep learning methods can be used in AI cybersecurity frameworks, with an emphasis on how well they can detect and counteract changing cyberthreats. The use of convolutional neural networks (CNNs) and deep neural networks (DNNs) for anomaly detection and pattern identification in network traffic is specifically discussed. The study also investigates the integration of AI-driven analytics to assess the performance and efficacy of security protocols, offering insights into optimizing defensive strategies against sophisticated cyber attacks. By leveraging AI capabilities, organizations can achieve proactive threat management, enhance incident response times, and fortify their networks against emerging cyber threats. This abstract sets the stage for a comprehensive exploration of AI's role in cybersecurity, highlighting its transformative impact on network security operations. © 2024 ieee.

关键词： Cyber attacks

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Approximate Convolutional Neural Networks Based on Dynamic Binding Windows

Approximate Convolutional Neural Networks Based on Dynamic B...

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CSI symposium on real-time and embedded Systems and Technologies (RTEST)

作者： Morteza Adelkhani Mehdi Sedighi Computer Engineering Amirkabir University of Technology Tehran Iran

ISBN: (数字)9798331529284

ISBN: (纸本)9798331529291

The rapid growth of applications focused on handling amounts of data has increased the demand, for computational power especially in areas such as machine learning and graph analysis within big data frameworks. While these applications have traditionally been run on data centers, they now encounter issues concerning security and quick access to data leading to a shift towards embedded systems with processing capacity. To tackle this challenge, we suggest a strategy to improve the efficiency of Convolutional Neural Networks (CNNs) on embedded systems through hardware-driven computing. Our innovative method, "Dynamic Binding Window" adjusts calculation precision dynamically within convolution layers based on feature map windows and layer positions reducing burden and energy usage without compromising accuracy. Our research demonstrates that this approach effectively overcomes the constraints of embedded systems allowing for real-time processing on devices. Comparative evaluations indicate enhancements in processing speed and energy efficiency showcasing the impact of our approach in fields, like autonomous vehicles that rely on swift and precise image analysis.

关键词： Data centers embedded systems Image analysis Machine learning Cyber-physical systems real-time systems Energy efficiency Convolutional neural networks Security Vehicle dynamics

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An FPGA-based real-time Optical Flow Accelerator for Recurrent All-Pairs Field Transforms

An FPGA-based Real-Time Optical Flow Accelerator for Recurre...

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ieee International symposium on Circuits and Systems (ISCAS)

作者： Xiaoliang Jia Hong Tang Xiqin Zheng Yingke Gao Longjun Liu National Key Laboratory of Human-Machine Hybrid Augmented Intelligence National Engineering Research Center for Visual Information and Applications and Institute of Artificial Intelligence and Robotics Xi'an Jiaotong University Beijing Institute of Control Engineering China Academy of Space Technology Beijing China

ISBN: (数字)9798350356830

ISBN: (纸本)9798350356847

Optical flow can capture the positional changes of pixels between two consecutive frames, thereby enabling the extraction of motion information for objects. real-time optical flow estimation is widely applied in tasks such as motion estimation, object detection, and tracking. Deep neural network-based optical flow algorithms have made a significant breakthrough in accuracy compared to traditional methods; however, their dense computational requirements hinder real-time deployment on resource-constrained embedded platforms. In this paper, we present ERAFT: a novel lightweight deep neural network architecture based on the Recurrent All-Pairs Field Transforms (RAFT) algorithm, which is more suitable for hardware deployment. Furthermore, we propose a specialized optical flow accelerator based on a prediction mechanism, enabling real-time and efficient optical flow estimation computations. The hardware accelerator was evaluated on the Xilinx VCK190 evaluation board. The results indicate that this accelerator achieves high accuracy on the Middlebury dataset, with speeds of up to 86 frames/s for 640 × 480 pixel images.

关键词： Accuracy Quantization (signal) Tracking Estimation Artificial neural networks Transforms real-time systems Optical flow Hardware acceleration Field programmable gate arrays

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Response-time Analysis of Fault-Tolerant Hard real-time Systems Under Global Scheduling

Response-time Analysis of Fault-Tolerant Hard Real-Time Syst...

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ieee International Conference on embedded and real-time Computing Systems and applications (RTCSA)

作者： Pourya Gohari Jeroen Voeten Mitra Nasri Eindhoven University of Technology (TU/e) Eindhoven The Netherlands

real-time systems are commonly used in safety-critical applications which require tasks to be completed before their deadlines, even in the presence of faults. Thus, fault tolerance becomes essential to ensure a certain level of reliability in safety-critical real-time systems [1]. To achieve fault tolerance in computer systems, redundancy can be implemented either in space (spatial redundancy) or time (time redundancy) [2]. Unlike spatial redundancy which involves increasing hardware resources, time redundancy focuses on re-execution or multiple executions of software on the same hardware resources [3] and therefore is better suited for embedded systems with limited cost and size constraints that are subject to transient faults more often than permanent faults [2], [4].

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Management Models for Wireless Communication Channel Interference Monitoring 8

Management Models for Wireless Communication Channel Interfe...

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8th International symposium on Multidisciplinary Studies and Innovative Technologies, ISMSIT 2024

作者： Pohasii, Serhii Holdobin, Serhii Brynza, Natalia Vilkhivska, Olga Bilotserkivskyi, Oleksandr Samorodov, Borys National Technical University 'Kharkiv polytechnic institute' Cybersecurity department Kharkiv Ukraine National Technical University 'Kharkiv polytechnic institute' Industrial and Biomedical electronics department Kharkiv Ukraine Kharkiv National University of Radio Electronics Department of Informatics and Computer Technology Simon Kuznets Kharkiv National University of Economics Department of Applied Mathematics Kharkiv Ukraine Simon Kuznets Kharkiv National University of Economics Department of Informatics and Computer Technology Kharkiv Ukraine National Technical University 'Kharkiv Polytechnic Institute' Business Trade and Logistics Department Kharkiv Ukraine V'N'Karazin Kharkiv National University Banking and Financial Technologies Department Kharkiv Ukraine

ISBN: (纸本)9798350354423

In modern wireless communication systems, ensuring reliable data transmission amidst interference is a critical challenge. Interference can arise from natural conditions, such as weather and terrain, or from artificial sources like other wireless devices sharing the same frequencies. This paper examines management models for monitoring interference in wireless communication channels using LoRa technology at two frequencies: 170 MHz and 433 MHz. By employing dual independent radio channels, communication redundancy is achieved, enhancing system resilience against interference. The STM32 microcontroller is utilized to provide intelligent control and real-time monitoring of the channels. Two distinct management models-feedback and cascade-are developed and compared in terms of transmission reliability, interference immunity, and resource efficiency. The findings provide insights into optimizing wireless communication systems, particularly for applications in critical sectors such as industrial sensor networks and transport systems. © 2024 ieee.

关键词： Microcontrollers

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Learning-Based realtime Synthetic Aperture Radar Imaging for embedded System on Satellite

Learning-Based Realtime Synthetic Aperture Radar Imaging for...

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ieee International symposium on Circuits and Systems (ISCAS)

作者： Tianyang Yu Bi Wu Weiqiang Liu College of Integrated Circuits Nanjing University of Aeronautics and Astronautics Nanjing China Key Laboratory of Aerospace Integrated Circuits and Microsystem Ministry of Industry and Information Technology China

ISBN: (数字)9798350356830

ISBN: (纸本)9798350356847

Spaceborne Synthetic Aperture Radar (SAR), due to its ability of all-weather and all-day sensing, is extensively utilized across various fields. realtime imaging on satellite is highly advantageous as it significantly reduces the communication cost and delay between satellite and ground station, making it exceptionally suitable for time-sensitive applications like maritime search and rescue. However, the limited computing power of embedded system on satellite, together with the substantial computational demands of traditional imaging algorithms, pose challenges for realtime imaging. To address these issues, a lightweight learning-based model with adjustable complexity is proposed for realtime imaging. Furthermore, we collect a large amount of real-world echo data from satellite and construct the first large-scale dataset, for training and evaluating the learning-based SAR imaging task. Experimental results and evaluation in the embedded system show that, the proposed learning-based model achieves up to 19× speedup than traditional algorithm.

关键词： Training embedded systems Satellites Imaging Radar imaging Radar polarimetry Data models Complexity theory Integrated circuit modeling Synthetic aperture radar

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