Since long, there is a rapid rise in energy-efficient appliances like electronics gadgets and microchip devices like health monitor wearable’s etc. The increased use of mentioned devices is built up via engineers to ...
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ISBN:
(数字)9798331531935
ISBN:
(纸本)9798331531942
Since long, there is a rapid rise in energy-efficient appliances like electronics gadgets and microchip devices like health monitor wearable’s etc. The increased use of mentioned devices is built up via engineers to perform enhancement of the different type of circuits. Circuit with high efficiency, low power consumption and good speed having less chip-area have been explored. Full adder is a primary component that is used in arithmetic circuits, which shows a key role in present digital signalprocessing system. Some of arithmetic circuits are integrators, comparators, multipliers etc. Important thing of this device is, it’s a main part of the recent communication systems and complex path of many network circuits. Therefore, optimizing its performance in early stages enhances the system's overall performance with high efficiency and greater accuracy. Reducing transistor count can often lead to a decrease in processing speed or computational power. The Cadence Virtuoso tool in the study simulates this adder circuit at 0.8v–1.2v VDD using 90 nano meter CMOS technology, with a comparatively short delay and the average consumption of power for a 0.9 V supply was remarkably low. The current method proved to be more efficient than existing hybrid designs.
In this paper, a novel modulation scheme called two-dimensional discrete cosine transform orthogonal frequency-division multiplexing (2D-DCT-OFDM), which extends the principles of OFDM modulation to a 2D domain is pro...
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ISBN:
(数字)9798331508050
ISBN:
(纸本)9798331508067
In this paper, a novel modulation scheme called two-dimensional discrete cosine transform orthogonal frequency-division multiplexing (2D-DCT-OFDM), which extends the principles of OFDM modulation to a 2D domain is proposed. Unlike traditional OFDM scheme, which relies solely on time-frequency processing, 2D-DCT-OFDM exploits an alternate 2D transform domain for information mapping and employs 2D-DCT operations along these dimensions for signalprocessing. Here, the design principles and performance analysis of the proposed 2D-DCT-OFDM modulation scheme are presented. Finally, the BER performance of the proposed 2D-DCT-OFDM scheme for different user equipment velocities are obtained and compared with the prior 1D and 2D modulation schemes (such as DFT-s-OFDM and OTFS) to get pertinent candidate waveform suggestions for beyond 5 th generation (B5G) and 6G cellular systems. Simulation results show that the 2D modulation schemes provide better BER performance in high-mobility scenarios. In addition, 2D-DCT-OFDM provides slightly better BER performance than other 2D modulation schemes under extreme mobility with significantly less computational complexity. Due to the simplicity, computational efficiency, ease of implementation, and power efficiency of 2D-DCT-OFDM, it is suitable for beyond 5G and 6G.
o accomplish relatively complex tasks of, such as, monitoring in vivo, information collected by different nano-sensors (NSs) is usually sent via multiple-access channels to fusion centers (FCs) for further processing....
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The article provides a comprehensive overview of the history of how signal-processing researchers have been effectively transforming signal-processing algorithms into efficient implementations. Starting from the early...
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The article provides a comprehensive overview of the history of how signal-processing researchers have been effectively transforming signal-processing algorithms into efficient implementations. Starting from the early days of analog circuits for signalprocessing, to digital signal processors (DSPs), to application specific DSPs and programmable DSPs, and to the trend of integrating a complete system on a single chip, this article provides a thorough coverage of the past and the present of design and implementation technology for signalprocessingsystems. Moreover, it presents the exciting challenges faced by the study of the design and implementation of current and future signalprocessing applications. Topics covered include milestones in signal-processing integrated circuits, the past and future of the signal processor, signalprocessing in consumer applications, and design automation for signalprocessing.
In this paper we present the hardware and software system architecture for a personal digital video player and recorder using a media processor and an MPEG-2 video codec.
ISBN:
(纸本)0780364880
In this paper we present the hardware and software system architecture for a personal digital video player and recorder using a media processor and an MPEG-2 video codec.
A design approach to create small-sized high-speed implementation of the new version of Secure Hash Algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degre...
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ISBN:
(纸本)0780393333
A design approach to create small-sized high-speed implementation of the new version of Secure Hash Algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed implementation does not introduce significant area penalty, compared to other competitive designs. However the achieved throughput presents an increase compared to commercially available IP cores that range from 43%-1830%.
In this paper a novel algorithm for computing the Dough Transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performances a...
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ISBN:
(纸本)0780364880
In this paper a novel algorithm for computing the Dough Transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performances and accuracy requirements. The algorithm is primarily developed to fit Field Programmable Gate Arrays (FPGA) implementation that have become a competitive alternative for high performance Digital signalprocessing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straight forward. This implementation may be achieved by generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of an HT parameter extractor for 8-bit image pixels is given.
This paper explains our experience in applying "higher" levels of abstraction for DSP based designs, Higher levels of abstraction allow us to describe digital radio designs in a more generic fashion, abstrac...
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ISBN:
(纸本)0780364880
This paper explains our experience in applying "higher" levels of abstraction for DSP based designs, Higher levels of abstraction allow us to describe digital radio designs in a more generic fashion, abstracted over carrier frequencies and data rates As such, specific instances of the radios can be compiled from our generic descriptions. In this way, we obtain rapid reconfiguration within a wide range of design specifications.
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter...
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ISBN:
(纸本)0780393333
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.
The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using Integer Linear Programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization al...
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ISBN:
(纸本)0780393333
The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using Integer Linear Programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.
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