An approach to the realisation of 2D FIR filters based on a novel radix-differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM ...
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ISBN:
(纸本)0780338065
An approach to the realisation of 2D FIR filters based on a novel radix-differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM coding system. Whereas the filter's coefficients are fed in digit serial fashion and specified using radix-2(n) arithmetic. The proposed approach provides a spectrum of architectures to allow a more flexible design trade off analysis between throughput rate and hardware cost.
This paper addresses a new kind of security vulnerable spots introduced by Network-on-chip (NoC) use in System-on-Chip (SoC) design. This study is based on the experience of a CAD framework for NoC design and proposes...
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ISBN:
(纸本)0780393333
This paper addresses a new kind of security vulnerable spots introduced by Network-on-chip (NoC) use in System-on-Chip (SoC) design. This study is based on the experience of a CAD framework for NoC design and proposes a classification of weaknesses with regard to usual routing and interface techniques. Finally design strategies are proposed and a new path routing technique (SCP) is introduced with the aim to enforce security.
This paper presents the implementation of the decorrelating (DECOR) transformation technique for low power FIR filtering cores. The technique was introduced in the past, but was not fully evaluated for its area, delay...
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ISBN:
(纸本)0780385047
This paper presents the implementation of the decorrelating (DECOR) transformation technique for low power FIR filtering cores. The technique was introduced in the past, but was not fully evaluated for its area, delay and power performance. Early evaluations did not consider the whole implementation and were merely based on either some analytical methods or high level simulation models. This paper presents the complete VLSI implementation of the technique and a study of its area, delay and power performance with different order of coefficient differences and various multiplier types. We show that although the technique achieves up to 47% power saving in the multiplier unit, the overall power saving is up to 25% with up to 24% increase in area.
This paper presents a new dataflow graph based approach for modelling, rapidly implementing, and performing high level optimization of embedded systems including dedicated pipelined hardware components. This overcomes...
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ISBN:
(纸本)0780385047
This paper presents a new dataflow graph based approach for modelling, rapidly implementing, and performing high level optimization of embedded systems including dedicated pipelined hardware components. This overcomes problems with current approaches which cannot achieve both pipelined circuit implementation and flexibility for high level optimization. A new dataflow modellng technique is presented, in conjunction with an enhanced component network synthesis approach. This technique is applied to a normalized lattice filter example demonstrating the capability for significant circuit performance improvements, a more intelligent directed synthesis flow and increased implementation flexibility.
Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet d...
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ISBN:
(纸本)9781424403820
Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet detector (PD) in terms of the requirement for the high hardware complexity. In this paper, we propose several low-cost design schemes for the PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented PD is less than half that of existing solutions.
In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where appli...
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ISBN:
(纸本)0780393333
In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design.
Multiplication over the field GF(2(m)) is computationally expensive, not least because the operation involves modulo reduction. It is typical to fix the field and field representation to improve performance, but some ...
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ISBN:
(纸本)9781424403820
Multiplication over the field GF(2(m)) is computationally expensive, not least because the operation involves modulo reduction. It is typical to fix the field and field representation to improve performance, but some applications need to operate over multiple fields. This work investigates the cost of this flexibility with application to elliptic curve cryptography (ECC), both analytically and empirically through FPGA implementation. A design methodology is presented for limiting the flexibility to a number of prescribed fields with the representation fixed for each, and the methodology is applied to the design of a bit-serial multiplier over GF(2(m)). FPGA implementation results are given;and it is shown that the practical advantage of the proposed approach is considerable in terms of speed versus area trade-off. In fact, only a 12.3% area overhead was incurred by the flexible implementation compared to the fixed field implementation, while still achieving the same speed performance.
The aim of this paper is to present a new approach to creating low-power high-performance DSP using delay-insensitive asynchronous circuits. To attain this, we pipeline the asynchronous circuit at logic gate level in ...
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ISBN:
(纸本)0780364880
The aim of this paper is to present a new approach to creating low-power high-performance DSP using delay-insensitive asynchronous circuits. To attain this, we pipeline the asynchronous circuit at logic gate level in such a way that every functional unit can be pipelined in many stages, up to as many as half the number of gate levels. Also, we want to integrate this approach with the traditional method to synthesise synchronous circuits. In order to achieve this, we create a new library of gates which satisfy the constraints that asynchronous design requires. Finally, we present the results after building a pipelined multiplier with both, synchronous and asynchronous, approaches.
The design and implementation of SP systems (DISPS) includes the development of software tools and methodologies to support the design of these complex systems. In its early days, DISPS focused on the hardware-based d...
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The design and implementation of SP systems (DISPS) includes the development of software tools and methodologies to support the design of these complex systems. In its early days, DISPS focused on the hardware-based design of SP algorithms to meet real-time requirements. This topic was often called very large-scale integration (VLSI) SP. The emphasis has gradually shifted to include software and hardware/software codesign and implementation aspects. Programmable digital signal processors (DSPs) and embedded central processing units (CPUs) are now popular for real-time SP, such as mobile phones. Field programmable gate array (FPGA)-based designs are also replacing application-specific integrated circuits (ASICs) in many applications.
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software def...
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ISBN:
(纸本)9781424403820
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, without compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) is presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance.
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