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检索条件"任意字段=IEEE Workshop on Signal Processing Systems Design and Implementation"
10815 条 记 录,以下是101-110 订阅
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EM-based channel estimation for space time block coded MIMO OFDM systems
EM-based channel estimation for space time block coded MIMO ...
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ieee workshop on signal processing systems design and implementation
作者: Karkhanechi, Haideh M. Levy, Bernard C. Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA
We propose a channel estimation technique based on an expectation maximization (EM) algorithm, for space-time block coded (STBC) multi-input njuldoutput (MIMO) OFDM systems. The channel estimation is done by decomposi... 详细信息
来源: 评论
signal processing in CMOS image sensors
Signal processing in CMOS image sensors
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ieee Annual workshop on signal processing systems: design and implementation
作者: Nair, R Raj, K Intel Corp Microproc Res Lab Santa Clara CA 95051 USA
A CMOS Image Sensor codenamed EYE2 developed on a standard Intel CMOS process and designed into the Intel 971 Camera Kit is described. EYE2 converted incident visual images into 10-bit digital data streams for still a... 详细信息
来源: 评论
Automating the verification of SDR base band signal processing algorithms developed on DSP/FPGA platform
Automating the verification of SDR base band signal processi...
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ieee workshop on signal processing systems design and implementation
作者: Kwan, Andrew Boumaiza, Slim Smith, Michael Ghannouchi, Fadhel Univ Calgary Dept Elect & Comp Engn Schulich Sch Engn 2500 Univ Dr NW Calgary AB T2N 1N4 Canada
This paper suggests an automated validation approach in testing advanced digital signal processing algorithms. These algorithms, which are intended for the implementation of the base band processor of Software defined... 详细信息
来源: 评论
Power and area efficient turbo decoder implementation for mobile wireless systems
Power and area efficient turbo decoder implementation for mo...
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ieee workshop on signal processing systems design and implementations (SiPS 05)
作者: Han, JH Erdogan, AT Arslan, T Univ Edinburgh Sch Engn & Elect Edinburgh EH9 3JL Midlothian Scotland
The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO dec... 详细信息
来源: 评论
A high-throughput area efficient FPGA implementation of AES-128 encryption
A high-throughput area efficient FPGA implementation of AES-...
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ieee workshop on signal processing systems design and implementations (SiPS 05)
作者: Brokalakis, A Kakarountas, AP Goutis, CE Univ Patras Comp Engn & Informat Dept Patras Greece
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter... 详细信息
来源: 评论
Image analysis and partitioning for FPGA implementation of image restoration
Image analysis and partitioning for FPGA implementation of i...
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ieee Annual workshop on signal processing systems: design and implementation
作者: Ogrenci, S Bazargan, K Sarrafzadeh, M Northwestern Univ Dept Elect & Comp Engn Evanston IL 60637 USA
In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adapt... 详细信息
来源: 评论
Battery-friendly design of signal processing algorithms
Battery-friendly design of signal processing algorithms
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ieee workshop on signal processing systems
作者: Raghavan, P Chakrabarti, C Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA
Portable systems today are designed with lowering the energy consumption as the primary design metric. This is unfortunate since maximizing battery lifetime is. a more appropriate metric, and lowering energy does not ... 详细信息
来源: 评论
Segmenetation based design of serial parallel multipliers
Segmenetation based design of serial parallel multipliers
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ieee workshop on signal processing systems design and implementations (SiPS 05)
作者: Bougas, P Tsirikos, A Kalivas, P Pekmestzi, KZ Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece
In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. ... 详细信息
来源: 评论
SIMULATION AND implementation TOOLS FOR signal-processing AND COMMUNICATION-systems
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ieee COMMUNICATIONS MAGAZINE 1994年 第7期32卷 36-40页
作者: SHANMUGAN, KS CADENCE DESIGN SYST INC SAN JOSECA
It is now possible to move easily from a top-level simulation model of a system toward its implementation. While this path is seamless and nearly complete for the digital implementation, gaps still exist for the imple... 详细信息
来源: 评论
implementation of complex-arithmetic heterodyne filter
Implementation of complex-arithmetic heterodyne filter
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ieee workshop on signal processing systems
作者: Soderstrand, MA Azam, A Sasidaran, D Nelson, KE Univ Calif Davis Davis CA 95616 USA
Heterodyne filters provide both tunable and adaptive filters with applications in narrow-band interference attenuation for spread-spectrum and other broad-band communications systems. A new complex-arithmetic version ... 详细信息
来源: 评论