We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is de...
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ISBN:
(纸本)9781424403820
We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is designed based on configurable processor. The configurable processor was used to complement the existing functional units with instruction extensions for the H.264 hardware kernel. Secondly, we profile the H.264 application to capture the amount of data traffic among modules. We will use this information to guide the placement of H.264 hardware modules in the dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in a dataflow architecture. With both our design methodologies, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time with maximum design flexibility
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of [1, 2]. The new architecture makes the implementation of mult...
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ISBN:
(纸本)9781424403820
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of [1, 2]. The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in ieee 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.
This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multi...
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ISBN:
(纸本)0780377958
This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perforin four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 mum HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.
In order to cope with the increasing number of functions that need to be implemented on a single chip as telecommunication products become more complex, a rapid trend towards programmable architectures as a base for d...
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ISBN:
(纸本)0780338065
In order to cope with the increasing number of functions that need to be implemented on a single chip as telecommunication products become more complex, a rapid trend towards programmable architectures as a base for digital signalprocessing (DSP) systems is occurring. The reason for this is that extremely complex algorithms and protocols must be implemented to economically use the available bandwidth for the next generation of wireless networks. The rapidly changing system requirements and design productivity and the intellectual property reuse are also promoting this trend.
A novel on-line Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) VLSI architecture is proposed. This architecture not only maintains the scaling-free property of the original,MSR-CORDIC, but also achieves the target of on-l...
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ISBN:
(纸本)9781424403820
A novel on-line Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) VLSI architecture is proposed. This architecture not only maintains the scaling-free property of the original,MSR-CORDIC, but also achieves the target of on-line angle computation. Compared with other existing CORDIC solutions, the proposed architecture is faster and more cost-efficient, especially for QRD-RLS filtering systems. Moreover, this on-line MSR-CORDIC can also be adopted by other rotation-based DSP applications.
Modular adders are fundamental arithmetic components that are employed in Residue Number System (RNS) based digital signalprocessing (DSP) systems. They are widely used in modular multipliers, residue to binary conve...
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ISBN:
(纸本)0780385047
Modular adders are fundamental arithmetic components that are employed in Residue Number System (RNS) based digital signalprocessing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies as well as a growing demand for portable electronics have brought power reduction to the forefront of modem day design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. In this paper, we propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13/mum standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay x area efficiency when compared to existing modular adder designs in the literature.
Fast and efficient operation is a major challenge for complex image processing algorithms executed in hardware. This paper describes novel algorithms for correcting optical geometric distortion in imaging systems, tog...
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ISBN:
(纸本)9781424403820
Fast and efficient operation is a major challenge for complex image processing algorithms executed in hardware. This paper describes novel algorithms for correcting optical geometric distortion in imaging systems, together with the architectures used to implement them in FPGA-based hardware. The proposed architecture produces a fast, almost real-time solution for the correction of image distortion implemented using VHDL HDL with a single XiIinx FPGA XCS3 10004 device. Using dedicated SRLC16 shift registers to build the synchronous FIFOs is an ideal utilization of the device resources available. The experimental results show that the barrel distortion can be quickly corrected with a very low residual error. The design can also be applied to other imaging processing algorithms in optical systems.
Architecture enhancements to the C6000 architecture have improved performance, reduced code size, lowered power, and increased compiler efficiency. In this work, benchmarks of DSP kernels and typical DSP applications ...
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ISBN:
(纸本)0780371453
Architecture enhancements to the C6000 architecture have improved performance, reduced code size, lowered power, and increased compiler efficiency. In this work, benchmarks of DSP kernels and typical DSP applications are used to compare commercially available DSPs in terms of cycle count, power, and compiler efficiency.
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines auto...
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ISBN:
(纸本)0780393333
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines automatically whether or not there are any faces in given images and, if so, returns the location and extent of each face. Next, FADECS uses neural network-based classifiers which allow the classification of several facial expressions from features that we develop and describe.
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise ...
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ISBN:
(纸本)0780393333
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise induced e.g. in FM radio links. Evaluation using a simulation application shows a significant increase in perceived audio quality compared to conventional compander systems.
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