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检索条件"任意字段=IEEE Workshop on Signal Processing Systems Design and Implementation"
10802 条 记 录,以下是121-130 订阅
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H.264 video decoder design: Beyond RTL design implementation
H.264 video decoder design: Beyond RTL design implementation
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ieee workshop on signal processing systems design and implementation
作者: Kim, Youngsoo Edmonson, William N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA
We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is de... 详细信息
来源: 评论
A reduced-complexity, scalable implementation of low density parity check (LDPC) decoder
A reduced-complexity, scalable implementation of low density...
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ieee workshop on signal processing systems design and implementation
作者: Zhu, Yuming Chen, Yanni Hocevar, Dale Goel, Manish Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA DSP Solut R&D Ctr Texas Inst Dallas TX 74243 USA
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of [1, 2]. The new architecture makes the implementation of mult... 详细信息
来源: 评论
implementation of a wireless multimedia DSP chip for mobile applications
Implementation of a wireless multimedia DSP chip for mobile ...
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ieee workshop on signal processing systems
作者: Heo, KL Sunwoo, MH Oh, SK Ajou Univ Sch Elect & Comp Engn Suwon 442749 South Korea
This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multi... 详细信息
来源: 评论
On core and more: A design perspective for system-on-chip
On core and more: A design perspective for system-on-chip
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1997 ieee workshop on signal processing systems (SiPS 97) - design and implementation
作者: Meyr, H RHEIN WESTFAL TH AACHEN RHEIN WESTFAL TH AACHENLAB INTEGRATED SYST SIGNAL PROCAACHENGERMANY
In order to cope with the increasing number of functions that need to be implemented on a single chip as telecommunication products become more complex, a rapid trend towards programmable architectures as a base for d... 详细信息
来源: 评论
On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems
On-line MSR-cordic VLSI architecture with applications to co...
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ieee workshop on signal processing systems design and implementation
作者: Yu, Tzu-Hao Yu, Chi-Li Jheng, Kai-Yuan Wu, An-Yeu Natl Taiwan Univ Grad Inst Elect Engn Dept Elect Engn Taipei 106 Taiwan
A novel on-line Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) VLSI architecture is proposed. This architecture not only maintains the scaling-free property of the original,MSR-CORDIC, but also achieves the target of on-l... 详细信息
来源: 评论
ELMMA: A new low power high-speed adder for RNS
ELMMA: A new low power high-speed adder for RNS
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ieee workshop on signal processing systems design and implementation
作者: Patel, RA Benaissa, M Powell, N Boussakta, S Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD S Yorkshire England
Modular adders are fundamental arithmetic components that are employed in Residue Number System (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary conve... 详细信息
来源: 评论
FPGA implementation of pipelined architecture for optical imaging distortion correction
FPGA implementation of pipelined architecture for optical im...
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ieee workshop on signal processing systems design and implementation
作者: Qiang, Lin Allinson, Nigel M. Univ Sheffield Dept Elect & Elect Engn Lab Image & Vis Engn Mappin St Sheffield S1 3JD S Yorkshire England
Fast and efficient operation is a major challenge for complex image processing algorithms executed in hardware. This paper describes novel algorithms for correcting optical geometric distortion in imaging systems, tog... 详细信息
来源: 评论
Higher performance and lower power enhancements to VLIW architectures
Higher performance and lower power enhancements to VLIW arch...
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ieee workshop on signal processing, systems design and implementation (SiPS 01)
作者: Gass, W Texas Instruments Inc Dallas TX USA
Architecture enhancements to the C6000 architecture have improved performance, reduced code size, lowered power, and increased compiler efficiency. In this work, benchmarks of DSP kernels and typical DSP applications ... 详细信息
来源: 评论
Detection and expression classification systems for face images (FADECS)
Detection and expression classification systems for face ima...
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ieee workshop on signal processing systems design and implementations (SiPS 05)
作者: Stathopoulou, IO Tsihrintzis, GA Univ Piraeus Dept Informat Piraeus 18534 Greece
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines auto... 详细信息
来源: 评论
Compander systems with adaptive preemphasis/deemphasis using linear prediction
Compander systems with adaptive preemphasis/deemphasis using...
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ieee workshop on signal processing systems design and implementations (SiPS 05)
作者: Holters, M Keiler, F Zölzer, U Peissig, J Helmut Schmidt Univ Hamburg Dept Signal Proc & Commun D-22043 Hamburg Germany
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise ... 详细信息
来源: 评论