This paper deals with the design of an all-digital receiver for the DVB-S standard in FPGA. We describe the implementation issues of the next stages: digital acquisition at intermediate frequency, downconversion to ba...
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ISBN:
(纸本)0780377958
This paper deals with the design of an all-digital receiver for the DVB-S standard in FPGA. We describe the implementation issues of the next stages: digital acquisition at intermediate frequency, downconversion to baseband, synchronization in time, and synchronization in frequency and phase. The high data rates needed by this all-digital architecture can only be achieved by a latest generation FPGA and with a careful design of each subsystem. So, for each stage we propose the most efficient design for Xilinx FPGAs in terms of area and throughput. And, finally, we present the implementation results of a complete DVB-S digital receiver on a Virtex-II Pro FPGA.
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D DWT with computation time as low as N-...
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This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D DWT with computation time as low as N-2/12 can be easily achieved for an N x N image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of N-2/3 and 2N(2)/3, the proposed designs can also save a large amount of multipliers and/or storage elements. It can also be used to implement those 2-D DWT traditionally suitable for lifting or flipping-based designs, such as (9,7) and (6,10) DWT. The throughput rate can be improved by a factor of 4 by the proposed approach, but the hardware cost increases by a factor of around 3. Furthermore, the proposed designs have very simple control signals, regular structures and 100% hardware utilization for continuous images.
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines auto...
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ISBN:
(纸本)0780393333
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines automatically whether or not there are any faces in given images and, if so, returns the location and extent of each face. Next, FADECS uses neural network-based classifiers which allow the classification of several facial expressions from features that we develop and describe.
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise ...
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ISBN:
(纸本)0780393333
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise induced e.g. in FM radio links. Evaluation using a simulation application shows a significant increase in perceived audio quality compared to conventional compander systems.
The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtain...
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ISBN:
(纸本)0780393333
The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtaining the excitation signal are analyzed and, based on this analysis, a new method is proposed. The influence of each method in the quality of the reconstructed wideband speech signal is evaluated by quantitative parameters of speech quality.
It is noted that signalprocessingdesigns for real-time large-scale systems are increasingly confronted with two conflicting objectives. The traditional objective of optimal design in low signal-to-noise ratio enviro...
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It is noted that signalprocessingdesigns for real-time large-scale systems are increasingly confronted with two conflicting objectives. The traditional objective of optimal design in low signal-to-noise ratio environments is confronted with the need for simplicity in implementation and speed of computation. The inclusion of high throughput and efficient hardware utilization as constraints on digital filter designs is considered. In particular, implementation of the design via an array processor is introduced. The concept of fast processing becomes synonymous with high throughout and efficient implementation on such a device. Using an array interpretation of the FFT structure, the retention of this highly efficient structure in a general design setting is demonstrated. For a typical signal extraction design, a constrained least-squares minimization is introduced to determine optimal enhancing filters with highly efficient array implementation.< >
This paper presents an architectural analysis for the MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between di...
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ISBN:
(纸本)0780385047
This paper presents an architectural analysis for the MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.
This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pi...
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ISBN:
(纸本)9781424403820
This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pipeline has been applied to the design, and pipeline stalls are avoided via instruction reordering and data forwarding. Three complex instructions are introduced to reduce the latency by reducing the overall number of instructions. The new processor shows improvements over previously reported designs in terms of throughput, latency and area. The higher clock frequencies and low latencies lead to the fastest point multiplication time reported in the literature. An FPGA implementation over GF(2(163)) is shown, which achieves a point multiplication time of 36.77 microseconds at 77.01 MHz on a Xilinx Virtex-E device- over 50% faster than the best figure previously reported.
In this paper receiver synthesis for nonlinearly amplified orthogonal frequency division multiplexing (OFDM) signal is presented. Optimal maximum-likelihood (ML) receiver is proposed and its computational complexity i...
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ISBN:
(纸本)0780377958
In this paper receiver synthesis for nonlinearly amplified orthogonal frequency division multiplexing (OFDM) signal is presented. Optimal maximum-likelihood (ML) receiver is proposed and its computational complexity is discussed. Further, sub-optimal receiver suitable for OFDM signals with large number of sub-carriers and high-order constellation is presented. The performance of optimal and sub-optimal receiver for nonlinearly amplified m-QAM-OFDM signal is studied by means of simulation.
An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a co...
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ISBN:
(纸本)0780393333
An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a computationally efficient method of extracting multiple channels belonging to two different communication standards, GSM and IS-95. The core of the system comprises of polyphase DFT filterbanks and very economical fractional rate-change filters. A flexible and efficient sample rate conversion method is also proposed that performs common rate changes using a shared hardware structure. Computational and hardware complexity comparisons are made based on results from a simulation test-bed developed for the proposed system.
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