An efficient design and VLSI implementation of a high data rate Medical Implant Communications Service (MICS) digital baseband transmitter for implantable medical devices is proposed in this paper. An orthogonal frequ...
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ISBN:
(纸本)9781457719219
An efficient design and VLSI implementation of a high data rate Medical Implant Communications Service (MICS) digital baseband transmitter for implantable medical devices is proposed in this paper. An orthogonal frequency division multiplexing (OFDM)-based multicarrier scheme is used to overcome the data rate limitation caused by the narrow bandwidth of 300 kHz. The proposed transmitter can support enhanced data rate by utilizing multiple channels simultaneously. Furthermore, to satisfy the MICS regulation, various schemes are applied including optimized subcarrier allocation for inverse fast Fourier transform (IFFT) and additional sidelobe suppression technique. The proposed transmitter with optimized hardware architecture is verified by VLSI implementation and it can support a maximum data rate of 4.86 Mbps, which is more than ten times faster than the previous systems.
Recursive filters are used frequently in digital signalprocessing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software solutions often are preferable for their s...
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ISBN:
(纸本)0780377958
Recursive filters are used frequently in digital signalprocessing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software solutions often are preferable for their speed of implementation and flexibility. However, contemporary DSPs are mostly not fast enough to perform filtering for high data-rates or large filters. A method to increase the computational power of a DSP without sacrificing efficiency is to use multiple processor elements controled by the single-instruction multiple-data (SIMD) paradigm. The parallelization of recursive algorithms is difficult, because of the data dependencies. We are using design methods for parallel procesor arrays to realize implementations that can be used on a parallel DSP. Further, we are focusing on the partitioning of the algorithm so that the realization can be used for different architectures. Consequences for the architecture are considered, too.
This paper presents high-radix CORDIC algorithms for high-speed sine and cosine computation. Since the CORDIC calculation takes O(n) steps for evaluating a function in n-bit precision, significant reduction of process...
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ISBN:
(纸本)0780338065
This paper presents high-radix CORDIC algorithms for high-speed sine and cosine computation. Since the CORDIC calculation takes O(n) steps for evaluating a function in n-bit precision, significant reduction of processing latency is required for real-time signalprocessing applications. In this paper, we present a unified approach to low-latency CORDIC implementation based on high-radix algorithms, and propose ''radix-2-4-8 CORDIC processor'', which achieves low-latency computation by changing radix during execution.
In this paper we investigate efficiencies that may be Introduced into the fault-tolerant MRRNS system by restricting the data sample polynomials to be even. We refer to this as the Symmetrical MRRNS (SMRRNS) technique.
ISBN:
(纸本)0780371453
In this paper we investigate efficiencies that may be Introduced into the fault-tolerant MRRNS system by restricting the data sample polynomials to be even. We refer to this as the Symmetrical MRRNS (SMRRNS) technique.
This paper presents a functional model based on a hierarchical architecture template meeting with Software Defined Radio System requirements (SDR systems). The concepts and mechanisms required to design future reconfi...
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ISBN:
(纸本)0780393333
This paper presents a functional model based on a hierarchical architecture template meeting with Software Defined Radio System requirements (SDR systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD Uplink, GSM Uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of an heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.
The topic of designing reliable and energy-efficiency multimedia systems in deep submicron technologies is addressed. First, various sources of noise and other non-idealities in current and future semiconductor techno...
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ISBN:
(纸本)0780371453
The topic of designing reliable and energy-efficiency multimedia systems in deep submicron technologies is addressed. First, various sources of noise and other non-idealities in current and future semiconductor technologies are described. Following this, two distinct design philosophies for implementing reliable and energy-efficient multimedia communication domains are presented. Both approaches optimize across algorithmic, architectural and circuit domains.
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the through...
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ISBN:
(纸本)0780393333
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.
The coarse-grained reconfigurable design paradigm provides, in a wide scope of design cases, effective support for adaptability, as required in modern embedded systems. The Reconfigurable Platform Composer Tool (RPCT)...
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ISBN:
(纸本)9781509033614
The coarse-grained reconfigurable design paradigm provides, in a wide scope of design cases, effective support for adaptability, as required in modern embedded systems. The Reconfigurable Platform Composer Tool (RPCT) project and its main outcome, the Multi-Dataflow Composer, aim at reducing the effort related with the design, mapping, optimization and prototyping of coarse-grained reconfigurable systems.
In this paper, a cost-effective implementation of a programmable filterbank front-end for speech recognition is presented. The objective has been to design a real-time bandpass filtering system with a filterbank of 16...
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ISBN:
(纸本)0780393333
In this paper, a cost-effective implementation of a programmable filterbank front-end for speech recognition is presented. The objective has been to design a real-time bandpass filtering system with a filterbank of 16 filters, with analog audio input and analog output. The output consists of 16 analog signals, which are the envelopes of the filter outputs of the audio signal. These analog signals are then led to an analog neural computer, which performs the feature-based recognition task. One of the main objectives has been to allow the user to easily change the filter specifications without affecting the remaining system, thus a software implementation of the filterbank was preferred. In addition, the neural computer requires analog input. Therefore, we implemented the filterbank on a PC, with the input A/D and the output D/A performed by the PC stereo soundcard. Since multiple analog outputs are necessary for the neural computer (one for each filter), it then follows that the soundcard output should contain the multiplexed 16 filter outputs, while a hardware module is needed for demultiplexing the soundcard output into the final 16 analog signals.
In this paper, we give a detailed presentation of a robust algorithm for detecting arcs of ellipse in a binary image. The characterization of such arcs of ellipse enables the identification between some video image el...
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ISBN:
(纸本)0780393333
In this paper, we give a detailed presentation of a robust algorithm for detecting arcs of ellipse in a binary image. The characterization of such arcs of ellipse enables the identification between some video image elements and the corresponding landmarks in a 3D model of the scene to be represented. This algorithm is based on a classical ellipse property that enables its parameters separation. It provides interesting results even in noisy images or when these arcs are small and partially hidden.
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