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共 10802 条记录，以下是151-160 订阅

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VLSI implementation of multiplier-free low power baseband filter for CDMA systems

VLSI implementation of multiplier-free low power baseband fi...

引用

ieee workshop on signal processing systems

作者： Lian, Y Yu, X Natl Univ Singapore Dept Elect & Comp Engn Singapore 119260 Singapore

ISBN: (纸本)0780377958

A multiplier-free baseband filter is proposed for the low power VLSI implementation in a Code Division Multiple Access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter structure involving a pair of even and odd length FIR filter with same bandedges. It is shown by means of example that the new structure not only achieves 45.8% savings in the number of multipliers, but also reduces the word length requirement for the coefficients of an IS-95 CDMA baseband filter. The VLSI implementation shows that the new structure reduces both the chip area and power consumption considerably compared with the direct-form implementation.

关键词： Attenuation Band pass filters Baseband Equalizers Finite impulse response filter IIR filters Multiaccess communication Passband Power filters Very large scale integration

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A frequency channelized adaptive wideband receiver for high-speed links

A frequency channelized adaptive wideband receiver for high-...

引用

ieee workshop on signal processing systems

作者： Feng, L Namgoong, W Univ So Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)0780377958

A new class of high-speed link receiver architecture that operates at a fraction of the on-chip clock frequency is proposed. Instead of time-interleaving multiple ADCs as is conventionally done, the received signal is channelized into multiple frequency subbands using a bank of mixers and lowpass filters. The proposed receiver architecture enjoys numerous implementation advantages. Based on the frequency channelized signals, an adaptive synchronization/detection scheme is described. An adaptive solution is necessary since the propagation channel and the analog analysis filters are generally not perfectly known and the symbol rate is incommensurate with the free running ADC sampling rate.

关键词： Band pass filters Bandwidth Channel bank filters Clocks Filter bank Frequency synchronization Sampling methods signal synthesis Transmitters Wideband

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Low-power floating-point encoding for signal processing applications.

Low-power floating-point encoding for signal processing appl...

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ieee workshop on signal processing systems

作者： Visalli, G Pappalardo, F ST Microelect Adv Syst Technol I-95121 Catania Italy

ISBN: (纸本)0780377958

ieee organization defined a standard for floating-point arithmetic, used by processing systems, in its directive 754 [1]. This directive encodes floating point numbers using a maximum of 64 bit: 23 bit of fractional as single precision format and 52 bit of fractional as double precision format. The new multimedia terminals require low-power applications;the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modem System-On-Chip. They might dissipate less power, using a reduced format representation. To verify this possibility, real systems simulate floating - point operations using different formats. In this conference paper, multimedia systems operate in different scenarios: wireless communication and image manipulation.

关键词： Arithmetic Convolutional codes Encoding Fading Gaussian noise Modems Multimedia systems Power system modeling signal processing Viterbi algorithm

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Efficient hardware realization of IRA code decoders

Efficient hardware realization of IRA code decoders

引用

ieee workshop on signal processing systems design and implementation

作者： Kienle, F Wehn, N Univ Kaiserslautern Microelect Syst Design Res Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)0780385047

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular Repeat-Accumulate (IRA) codes belong to the class of Low-Density Parity-Check (LDPC) codes and can even outperform the recently introduced Turbo-Codes of current communication standards. implementation complexity like area, achievable throughput of these channel coding schemes will have a major impact on the decision of standardization committees. In this paper we investigate implementation issues of IRA codes and analyze the strong interdependency of code performance and architectural dependencies, like throughput and area. We present an architecture template which is capable to decode hardware optimized IRA codes which can outperform Turbo-Codes (TC). We demonstrate this new approach through instances synthesized in a 0.13 mum technology.

关键词： decoding parity check codes channel coding LDPC codes linear-time encoding complexity encoder IRA code decoder hardware implementation irregular repeat-accumulate codes low-density parity-check codes implementation area achievable throughput hardware optimized IRA codes 0.13 micron Channel coding low density parity check codes parity check codes DECODING ENCODER Codes

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INVERSION OF NONLINEAR AND TIME-VARYING systems

INVERSION OF NONLINEAR AND TIME-VARYING SYSTEMS

引用

ieee Digital signal processing workshop/ieee signal processing Education workshop (DSP/SPE)

作者： Baran, Thomas A. Oppenhiem, Alan V. MIT Digital Signal Proc Grp Cambridge MA 02139 USA

ISBN: (纸本)9781612842271

This paper is concerned with the inversion of implementations for systems that may generally be nonlinear and time-varying. Specifically, techniques are presented for modifying an implementation of a forward system, represented as an interconnection of subsystems, in such a way that an implementation for the inverse system is obtained. We focus on a class of modifications that leave subsystems in the inverse system unchanged with respect to those in the forward implementation. The techniques are therefore well-suited to the design of matched pre-emphasis and de-emphasis filters, as approximations due to coefficient quantization in the forward system are naturally matched in the inverse. In performing the inversion, an explicit input-output characterization of the system is not required, although the forward system must be known to be invertible. The techniques are applied to the inversion of nonlinear and time-varying systems, as well as to the problem of sparse matrix inversion.

关键词： Inverse systems nonlinear filters nonlinear systems signal flow graphs

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FPGA implementation of adaptive filters based on GSFAP using log arithmetic

FPGA implementation of adaptive filters based on GSFAP using...

引用

ieee workshop on signal processing systems design and implementation

作者： Tichy, Milan Schier, Jan Gregg, David Acad Sci Czech Republ Inst Informat Theory & Automat CR-18208 Prague Czech Republic Univ Dulbin Trinity Coll Dublin Ireland

ISBN: (纸本)9781424403820

Adaptive filters are used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. The GSFAP algorithm, discussed in the paper, is characterized by convergence superior to the popular NLMS, with only slightly higher complexity. The paper deals with floating-point-like implementation of algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The design is crafted to make efficient use of the pipelined logarithmic addition units. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and it allows a higher signal sampling rate (around 70 kHz) for the corresponding filter orders, GSFAP has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

关键词： Digital signal processing

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design and implementation of JPEG 2000 codec with bit-plane scalable architecture

Design and implementation of JPEG 2000 codec with bit-plane ...

引用

ieee workshop on signal processing systems design and implementation

作者： Chang, Yu-Wei Chen, Chih-Chi Chen, Chun-Chia Fang, Hung-Chi Chen, Liang-Gee Natl Taiwan Univ Grad Inst Elect Engn Dept Elect Engn DSP IC Design Lab Taipei Taiwan

ISBN: (纸本)9781424403820

In this paper, an area-efficient JPEG 2000 codec is implemented. on 6.1 mm(2) with 0.18 mu m CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable or processing 78 MS/s for lossy coding at 1 bpp and 50 MS/s for lossless coding. Four techniques are used to implement this chip. The pre-compression rate-distortion optimization (pre-RDO) determine truncation points before coding to reduce computations for the EDC. The dataflow conversion and embedded compression reduces the tile memory bandwidth. The bit-plane parallel context formation enables scalable bit-plane coding. Experimental results shows this chip has higher area efficiency than the previous works.

关键词： Codes (symbols)

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System integration issues for set-top box

System integration issues for set-top box

引用

1997 ieee workshop on signal processing systems (SiPS 97) - design and implementation

作者： Gass, WK Texas Instruments Inc Dallas United States

ISBN: (纸本)0780338065

In a cost sensitive consumer electronics market, the most cost-efficient implementation of the digital satellite set-top box is required in order to be competitive. The system functionality and the implementation rational of the set-top box is described. Tradeoffs regarding hardware vs. software implementation are examined. Examples of how the system design affects the size and bandwidth of the memory requirements are given. Although the current generation of processors are capable of implementing real-time video decoding, they still are not a cost-effective solution for the digital set-top box.

关键词： Satellite communication systems

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Efficient IMDCT core designs for audio signal processing

Efficient IMDCT core designs for audio signal processing

引用

ieee workshop on signal processing systems

作者： Wu, PS Hwan, YT Natl Yunlin Univ Sci & Technol Dept Elect Engn Toulin 640 Yunlin Taiwan

ISBN: (纸本)0780377958

Filter bank processing techniques based on MDCT/IMDCT have been widely adopted in various audio codec standards. Most published IMDCT computing algorithms focus mainly on either the reduction of computing complexity but overlook the hardware realization issues, e.g. memory access complexity and the efficient mapping of computing kernel. In this paper, by exploiting the symmetric properties in computation, we first convert an N-point IMDCT to an N/2-point DCT-II problem. Fast DCT-II computing scheme is next derived and the overall scheme is further optimized to remove redundancy. Based on the proposed fast IMDCT computing scheme, a novel design mapping is developed to minimize memory access complexity without stalling the pipelined computation. The mapping features simple address generation, small temporary storage size and low access bandwidth. Performance analyses show that, given the same hardware resource allocation, the proposed design can outperform other well known IMDCT designs in terms of memory storage size, computing latency or fixed point implementation error.

关键词： Code standards Codecs Discrete cosine transforms Filter bank Hardware Kernel Redundancy signal design signal processing signal processing algorithms

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design Kernel Exploration Using QBF-Based Boolean Matching

Design Kernel Exploration Using QBF-Based Boolean Matching

引用

ieee International workshop on signal processing systems (SiPS)

作者： Preusser, Thomas B. Erxleben, Fredo Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781509033614

The synthesis and mapping of user designs to configurable hardware is typically performed by heuristics. These approaches analyze the decomposability of the combinational user functions as a starting point and derive appropriate mappings to LUT structures or pull them in from pre-computed implementation libraries. In everyday use, this generally achieves a very competitive trade-off between the time spent for the synthesis and the quality of the produced implementations. A higher pressure on the optimality of an implementation exists when implementation libraries are generated or when critical kernels that are extensively duplicated in a massively parallel design are implemented. In these cases, a formal statement that an implementation within fewer LUTs or a smaller combinational depth is strictly impossible is very valuable. We present a tool that formulates the task of mapping a user design to a configurable hardware structure as a quantified boolean formula (QBF). It then uses a QBF solver to either compute an implementing configuration or to know for sure that the desired functionality cannot be implemented within the provided hardware. In the context of this tool, we also describe different approaches to model configurable interconnects and present the impact of these modelling approaches on the time needed to solve the mapping tasks.

关键词： Mapping

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