Today's programmable chips are segregated into five classes and comparison among these classes are given. Due to hardware comparison, Domain Specific Programmable chips have great advantage on realizing complex mu...
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ISBN:
(纸本)0780338065
Today's programmable chips are segregated into five classes and comparison among these classes are given. Due to hardware comparison, Domain Specific Programmable chips have great advantage on realizing complex multimedia functions over general purpose processors. Future applications for such DSP chips are also described through our experience on Silicon Terminal Series.
Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. Thi...
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ISBN:
(纸本)0780364880
Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. This leads to a pessimistic estimation of processor speed, and the engineering efforts spent optimizing such paths can not improve the performance of the chip. In the past, we demonstrated initial results of how ATPG technique can be used to eliminate false paths efficiently[1]. Due to the gap between the physical design on which the static timing analysis of the chip is based and the test view on which ATPG technique is applied to eliminate false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this paper, we will fully analyze all the timing paths using the ATPG technique overcoming the gap between the testing and timing analysis techniques. We applied our method on the second G4(1) PowerPC(TM).
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing...
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ISBN:
(纸本)0780393333
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing Probabifity, and Mean Acquisition Time of the proposed timing synchronization scheme are compared with the existing method of 141 to demonstrate the excellence of the proposed scheme. MSE (Mean Square Error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.
This paper presents a new algorithm for 2D nonseparable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of filter of wavelet transform written as (LxM) tap 2D filter. ...
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ISBN:
(纸本)0780377958
This paper presents a new algorithm for 2D nonseparable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of filter of wavelet transform written as (LxM) tap 2D filter. The results are efficient architectures for real time signalprocessing, which don't require transpose memory for 2D processing of data. The proposed architecture exploits in place implementation inherit from the algorithm and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in architecture is scheduled carefully by pipelining the lifted steps, which allows two or four times faster processing than the direct implementation. The architecture therefore allows lowering the clock frequency by two/four. The proposed architecture operates at high speed/consumes low power and has reduced computational complexity as compared to already published filter and lifted based bi-orthogonal wavelet architectures.
As the increasing size of private or online electronic text collections reaches several terabytes, finding relevant information has become a real challenge for modern computerized systems. The low classification or th...
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ISBN:
(纸本)0780393333
As the increasing size of private or online electronic text collections reaches several terabytes, finding relevant information has become a real challenge for modern computerized systems. The low classification or the data stored in repositories exempted from quality control justifies the need for approximate matching methods maintaining the efficiency or the retrieval and accuracy of the results. Moreover, because the average bandwidth or the main memory is crucial for system performance, development of digital VLSI (Very Large Scale Integration) architectures for low-level and very high throughput data processing has been a main issue in this work. Thus this paper presents the hardware realization of a text search engine using bit-parallelism and a fast serial processing of the database information. It describes the internal architecture of an associative processor which was efficiently implemented and tested on an FPGA (Field Programmable Gate Array) platform, acting yet as an external hardware accelerator for standard PC solutions.
In this paper, we introduce a polyphase implementation and design of an oversampled K-channel generalized DFT (GDFT) filter bank, which can be employed for subband adaptive filtering, and therefore is required to have...
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ISBN:
(纸本)0780349970
In this paper, we introduce a polyphase implementation and design of an oversampled K-channel generalized DFT (GDFT) filter bank, which can be employed for subband adaptive filtering, and therefore is required to have a low aliasing level in the subband signals. A polyphase structure is derived which can be factorized into a real valued polyphase network and a GDFT modulation. For the latter, an FFT realization may be used, yielding a very inexpensive polyphase implementation for arbitrary integer decimation ratios N less than or equal to K. We also present an analysis underlining the efficiency of complex valued subband processing. The design of the filter bank is completely based on the prototype filter and solved using a fast converging iterative least squares method, for which we give examples. The design specifications closely correspond with performance limits of subband adaptive filtering, which are under-pinned by simulation results.
In this paper, novel design and implementation decompositions are found to arise for a recently offered minimum mean squared error (MMSE) linear predictive transform (LPT) estimator when certain symmetry conditions ar...
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In this paper, novel design and implementation decompositions are found to arise for a recently offered minimum mean squared error (MMSE) linear predictive transform (LPT) estimator when certain symmetry conditions are satisfied by the first- and second-order statistics used to design the estimator. This results in a decomposed LPT estimator whose design and implementation computational effort is significantly less than that of the original estimator.
Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be desc...
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ISBN:
(纸本)0780338065
Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be described to demonstrate how to overcome this gap. A more radical solution will then be described which no longer defines programming as a procedure that operates on data, but as a specification of data sets that require transformations. While this can be emulated on top of the CSP model, more efficient hardware implementations are possible. The author speculates that this could result in architectures that are hard real-time and optimised by design.
An efficient technique for hierarchical image coding is proposed, which divides an image into its multiple resolution versions with minimum hardware cost. Since the proposed technique uses discrete cosine transform (D...
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ISBN:
(纸本)0780377958
An efficient technique for hierarchical image coding is proposed, which divides an image into its multiple resolution versions with minimum hardware cost. Since the proposed technique uses discrete cosine transform (DCT) over each frequency band data, obtained directly from DCT domain by multiplying pre-calculated matrices, compatibility can be preserved easily with DCT-based image/video standards. First, we present the 1-D case, followed by an extension to the 2-D case. The proposed coder is observed to result in significant reduction of memory and computational complexity requirement with higher peak signal to noise ratio (PSNR), when compared with traditional hierarchical image coding method.
In this paper we shall present an NDA (Non Data Aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (Additive White Gaussian Noise). It shall be shown that the detector allows the car...
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ISBN:
(纸本)9781424403820
In this paper we shall present an NDA (Non Data Aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (Additive White Gaussian Noise). It shall be shown that the detector allows the carrier synchronization PLL (Phase Locked Loop) to achieve optimal performance during both the acquisition and tracking operation modes. The conditions necessary for this optimality to be achieved will be discussed, and it shall be shown that they are quite reasonable and allow the proposed detector to be implemented in many contemporary M-PSK receivers. The optimal behaviour of the PLL will be shown to hold regardless of the SNR (signal-to-Noise Ratio) and of the AGC (Automatic Gain Control) circuit behaviour. Moreover, the proposed detector has a simple fixed-point structure that can be feasibly implemented using few hardware resources within contemporary FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits). Finally, operation of the proposed detector under frequency-flat slow signal fading conditions is also discussed.
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