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Distributed and Scalable Uplink processing for LIS: Algorithm, Architecture, and design Trade-Offs

ieee TRANSACTIONS ON signal processing 2022年 70卷 2639-2653页

作者： Sanchez, Jesus Rodriguez Rusek, Fredrik Edfors, Ove Liu, Liang Lund Univ Dept Elect & Informat Technol S-22363 Lund Sweden

The Large Intelligent Surface (LIS) is a promising technology in the areas of wireless communication, remote sensing and positioning. It consists of a continuous radiating surface located in the proximity of the users, with the capability to communicate by transmission and reception (replacing base stations). Despite its potential, there are numerous challenges from an implementation point of view, with the interconnection data-rate, computational complexity, and storage the most relevant ones. In order to address these challenges, hierarchical architectures with distributed processing techniques are envisioned to be relevant for this task, while ensuring scalability. In this work we perform algorithm-architecture codesign to propose two distributed interference cancellation algorithms, and a tree-based interconnection topology for uplink processing. We also analyze the performance, hardware requirements, and architecture trade-offs for a discrete LIS, in order to provide concrete case studies and guidelines for efficient implementation of LIS systems.

关键词： Backplanes signal processing algorithms Antenna arrays Massive MIMO Surface waves Transmitting antennas Baseband Large intelligent surface LIS distributed processing algorithm-architecture codesign equalization inter-connection data-rate

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A Sub-mW Cortex-M4 Microcontroller design for IoT Software-Defined Radios

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS

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ieee OPEN JOURNAL OF CIRCUITS AND systems 2023年 4卷 165-175页

作者： Xhonneux, Mathieu Louveaux, Jerome Bol, David Catholic Univ Louvain ICTEAM Inst B-1348 Louvain la neuve Belgium

We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 - 332 mu W) for the digital signal processing of the software-defined radios.

关键词： Internet of Things wireless communications microcontrollers low-power wide area networks reconfigurable devices software defined radio

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Low PAPR MIMO-OFDM design Based on Convolutional Autoencoder

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ieee TRANSACTIONS ON COMMUNICATIONS 2024年第5期72卷 2779-2792页

作者： Huleihel, Yara Permuter, Haim H. Ben Gurion Univ Negev Dept Elect Engn IL-8486208 Beer Sheva Israel Ben Gurion Univ Negev Dept Elect & Comp Engn IL-84105 Beer Sheva Israel

An enhanced framework for peak-to-average power ratio (PAPR) reduction and waveform design for Multiple-Input-Multiple-Output (MIMO) orthogonal frequency-division multiplexing (OFDM) systems, based on a convolutional-autoencoder (CAE) architecture, is presented. The end-to-end learning-based autoencoder (AE) for communication networks represents the network by an encoder and decoder, where in between, the learned latent representation goes through a physical communication channel. We introduce a joint learning scheme based on projected gradient descent iteration to optimize the spectral mask behavior and MIMO detection under the influence of a non-linear high power amplifier (HPA) and a multipath fading channel. The offered efficient implementation novel waveform design technique utilizes only a single PAPR reduction block for all antennas. It is throughput-lossless, as no side information is required at the decoder. Performance is analyzed by examining the bit error rate (BER), the PAPR, and the spectral response and compared with classical PAPR reduction MIMO detector methods on 5G simulated data. The suggested system exhibits competitive performance when considering all optimization criteria simultaneously. We apply gradual loss learning for multi-objective optimization and show empirically that a single trained model covers the tasks of PAPR reduction, spectrum design, and MIMO detection together over a wide range of SNR levels.

关键词： Peak to average power ratio MIMO communication Optimization Wireless communication Transmitting antennas Symbols Antennas Deep learning autoencoder multiple-input-multiple-output orthogonal frequency-division multiplexing peak-to-average power ratio wireless signal processing

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A Multimedia Framework for Continuum Robots: Systematic, Computational, and Control Perspectives

A Multimedia Framework for Continuum Robots: Systematic, Com...

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2024 International Symposium on Intelligent signal processing and Communication systems, ISPACS 2024

作者： Hsieh, Po-Yu Hou, June-Hao Graduate Institute of Architecture National Yang Ming Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9798350389210

Continuum robots, which often rely on interdisciplinary and multimedia collaborations, have been increasingly recognized for their potential to revolutionize the field of human-computer interaction (HCI) in varied applications due to their adaptive, responsive, and flexible characteristics. Despite their promises, the lack of an integrated framework poses a significant limitation for both users and developers, resulting in inefficiency and complexity during preliminary developments. Thus, this paper introduces a unified framework for continuum robotic systems that addresses these challenges by integrating system architecture, dynamics computation, and control strategy within a computer-aided design (CAD) platform. The proposed method allows for efficient modeling and quick preview of the robot performance, and thus facilitating iterative design and implementation, with a view to enhancing the quality of robot developments. © 2024 ieee.

关键词： Machine design

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Advancements in Operational Transconductance Amplifiers (OTAs) for design, Applications & Performance Optimization Techniques with Hardware implementation 3

Advancements in Operational Transconductance Amplifiers (OTA...

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3rd ieee International Conference of Electron Devices Society Kolkata Chapter, EDKCON 2024

作者： Pramath, V. Pavithra, G. Ninawe, Swapnil S. Manjunath, T.C. Bengaluru India Dayananda Sagar College of Engineering Department of Electronics & Communication Engineering Karnataka Bangalore India Rajarajeswari College of Engineering Department of Computer Science & Engineering IoT Cyber Security & Block Chain Technology Karnataka Bangalore India

ISBN: (纸本)9798350374643

This research paper presents the design and simulation of a novel architecture for Multiple Path Fully Differential Operational Transconductance Amplifiers (OTAs) with a Dual Flipped Voltage Follower, specifically developed for VLSI-based signal processing applications. Utilizing advanced 50nm CMOS technology and Cadence tools, the proposed OTA architecture achieves enhanced performance and versatility in handling various signal processing tasks. design employs multiple signal paths, which contribute to improvements in bandwidth, gain, and linearity, while also effectively minimizing common-mode noise. This multi-path approach ensures better signal integrity and reliability in high-performance applications. The integration of the Dual Flipped Voltage Follower further strengthens the OTA's stability and dynamic range, allowing it to operate seamlessly in high-speed VLSI systems. The architecture is designed to cater to the rigorous demands of modern signal processing, where precision and speed are critical. Extensive simulation studies were conducted to validate the OTA design, and the results demonstrate that the proposed approach meets or exceeds the stringent requirements of today's signal processing applications. Findings of this research contribute to the ongoing advancements in VLSI design methodologies and provide a promising solution for engineers working with nanoscale CMOS technologies. Simulation results using Cadence tools highlights effectiveness and robustness of proposed design. © 2024 ieee.

关键词： CMOS integrated circuits

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design and implementation of Doppler Centroid Estimation with Quality Index for Real-Time SAR Imaging 20

Design and Implementation of Doppler Centroid Estimation wit...

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20th Asia-Pacific Conference on Circuits and systems

作者： Chen, Po-Ta Tsai, Pei-Yun Lee, Sz-Yuan Natl Cent Univ Dept Elect Engn Taoyuan Taiwan Natl Taiwan Univ Grad Sch Adv Technol Taipei Taiwan Taiwan Space Agcy Hsinchu Taiwan

ISBN: (纸本)9798350378788;9798350378771

Doppler centroid estimation is essential for synthetic aperture radar (SAR) imaging in stripmap mode. However, the quality of estimation is influenced by the scene significantly. We propose to use dispersion of phase differences from beat signals of adjacent range lines as a quality index for selecting reliable estimates. The improvement in success rate demonstrates its effectiveness compared to the conventional quality indices such as the signal-to-noise ratio (SNR) and contrast. A hardware accelerator for real-time Doppler parameter estimation including baseband Doppler centroid and Doppler ambiguity estimations is then implemented. It is integrated in the range Doppler algorithm (RDA) imaging processor and supports configurability. The range compressed data in the frequency domain arc used as the input. Several hardware design techniques are adopted to reduce buffer sizes, computation complexity, and latency. The processing time of our Doppler centroid estimator for an 8Kx8K image is 0.082s at 100MHz operating frequency.

关键词： Synthetic Aperture Radar (SAR) Doppler centroid estimation multilook beat frequency algorithm (MLBT) real-time processing

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design and implementation of DOA Algorithms for Smart Antenna systems 25

Design and Implementation of DOA Algorithms for Smart Antenn...

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25th International Carpathian Control Conference (ICCC)

作者： Shouffi, Ousama Shaglil, Ibrahim Stayanova, Krassimira Benotsmane, Rabab Univ Miskolc Dept Informat Miskolc Hungary Bulgarian Acad Sci Inst Informat & Commun Technol Sofia Bulgaria Univ Miskolc Inst Automat & Infocommun Miskolc Hungary

ISBN: (纸本)9798350350708;9798350350715

Wireless communication systems have evolved rapidly to meet the ever-increasing demands for connectivity, speed, and reliability. A pivotal advancement in this domain is the integration of smart antennas, which harness sophisticated signal processing and antenna technology to enhance communication system performance. This research focuses on the development and implementation of algorithms to estimate received signals in a smart antenna system, with a primary emphasis on Direction of Arrival (DOA) algorithms for Beamforming systems. The core of our work focuses on a model designed to exploit DOA algorithms, a fundamental tool in smart antenna technology, to refine the reception and transmission of signals. Within this smart antenna system, received signals undergo meticulous processing to determine their precise direction and angles. The ability to ascertain the correct signal direction is integral to the reformation of beam patterns in Beamforming systems, aligning them with the estimated angles. This alignment optimizes signal reception, minimizes interference, and enhances the overall efficiency of the wireless communication system.

关键词： wireless communication smart antenna Direction of Arrival (DOA) beamforming

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FPGA implementation of Sphere Decoding in MIMO systems: Challenges Solutions and design issues 3

FPGA Implementation of Sphere Decoding in MIMO Systems: Chal...

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3rd ieee International Conference on Recent Advances in systems Science and Engineering, RASSE 2023

作者： Girija, M.G. Sudha, T. Cherian, Riboy Saintgits College of Engineering Department of ECE Kottayam India APJ Abdul Kalam Technological University Kerala India

ISBN: (纸本)9798350341676

Multiple-input multiple-output (MIMO) systems have gained significant attention due to their ability to enhance wireless communication performance. A promising method for symbol detection that offers better performance than conventional detection algorithms is the incorporation of sphere decoding in MIMO systems. Field Programmable Gate Array (FPGA)-based implementations become increasingly popular for real-Time and power-efficient signal processing. This paper presents a comprehensive study on the challenges, solutions, and design issues encountered in FPGA-based sphere decoding implementations for MIMO systems. The findings contribute to the growing body of knowledge on FPGA-based MIMO signal processing and offer valuable insights for researchers and engineers aiming to deploy high-performance and resource efficient MIMO systems in practical applications. The FPGA implementation in MIMO systems holds the promise of revolutionizing wireless communication by satisfying the growing need for dependable connectivity and faster data rates. © 2023 ieee.

关键词： MIMO systems

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An Efficient Algorithm design of MIMO-OFDM systems for Co-Channel Interference Mitigation 24

An Efficient Algorithm Design of MIMO-OFDM Systems for Co-Ch...

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24th ieee International workshop on signal processing Advances in Wireless Communications, SPAWC 2023

作者： Liu, Junkai Wen, Ziyu Zhang, Wei Jiang, Yi Fudan University School of Information Science and Technology Department of Communication Science and Engineering Shanghai China

ISBN: (纸本)9781665496261

In this paper, we present an efficient algorithm of co-channel interference (CCI) mitigation for uplink multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) systems by exploiting the smoothness of OFDM channels in the frequency domain. Given the pilot sequences being synchronized, the proposed algorithm computes the time-domain equalizer by solving a high-dimensional block Toeplitz system, requiring no explicit estimation of the channels and interference-plus-noise covariance matrices (ICMs). We also present a technique to determine the order of equalizer, which is adaptive to the length of the time-domain finite-impulse-response (FIR) channel. The numerical experiments conducted on a fifth-generation (5G) new radio (NR) simulator show that the proposed algorithm outperforms the state-of-the-art schemes with even lower computational complexity. © 2023 ieee.

关键词： Orthogonal frequency division multiplexing

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Analysis of Optimization on Sparse Matrix Vector Multiplication Model Application in Digital signal processing 3

Analysis of Optimization on Sparse Matrix Vector Multiplicat...

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3rd ieee International Conference on Electrical Power and Energy systems, ICEPES 2024

作者： Shaji, Alden C Khare, Kavita Maulana Azad National Institute of Technology Electronics & Communication Engineering Department Bhopal India

ISBN: (纸本)9798350390728

Conventional digital signal processing (DSP) technology, utilizing DSP and FPGA, excels in real-time signal processing but faces limitations in handling large-scale data and achieving high frequency resolution. This restricts its effectiveness for tasks involving offline data processing, analysis, and mining in applications with extensive data volumes. Some of the SpMV applications in image editing operations like linear filtering, resizing and mixing are reformulated in the SpMV multiplication form. The growing complexity of applications and the demand for top-notch digital data necessitate a boost in processing power. With energy efficiency becoming a critical concern, there is research on designing SpMV algorithms that minimize energy consumption. This is particularly relevant for embedded DSP systems and applications where power efficiency is a key consideration. A comparative study of High-Level Synthesis (HLS) techniques to reduce the power consumption and resource utilization conducted on Xilinx-Zynq 7000 FPGA is presented. This paper explores various HLS pragmas techniques using OpenCL framework applied on Sparse Matrix Vector Multiplication (SpMV) kernel for optimizing power efficiency and resource utilization. HLS has emerged has a pivotal technology for simplifying the design process of complex digital systems by allowing developers to work at higher levels of abstraction, using high-level programming languages. From the analysis, identified the best optimization technique for the low power and the minimum resource utilization for the SpMV implementation on FPGA hence it can be more useful for applications in the field of CNN. © 2024 ieee.

关键词： High level synthesis

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