Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet d...
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ISBN:
(纸本)9781424403820
Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet detector (PD) and time-frequency code synchronization, in terms of the requirement for fast synchronization for the frequency hopping, the extremely low receiver sensitivity, and the high hardware complexity. hi this paper, we firstly systematically analyze the differences between MB-OFDM and conventional OFDM systems, and then propose a band tracking PD (BT-PD) that can cope with a worse-case multipath channel SNR of -8.4 dB with a packet detection error rate of less than 10(-5).
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing...
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ISBN:
(纸本)0780393333
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing Probabifity, and Mean Acquisition Time of the proposed timing synchronization scheme are compared with the existing method of 141 to demonstrate the excellence of the proposed scheme. MSE (Mean Square Error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.
Real time signal, image, and control applications have very important time constraints, involving the use of several powerful numerical calculation units. The aim of our project is to develop a fast and automatic prot...
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ISBN:
(纸本)0780377958
Real time signal, image, and control applications have very important time constraints, involving the use of several powerful numerical calculation units. The aim of our project is to develop a fast and automatic prototyping process dedicated to parallel architectures made of both PC and several last generation Texas Instruments digital signal processors : TMS320C6X DSP. The process is based on SynDEx, a CAD software improving algorithm implementation onto multi-processor architectures by finding the best matching between an algorithm and an architecture. SynDEx kernels for automatic PC and DSP dedicated code generation have been developed with the new SynDEx functionalities. A full coding application (LAR) illustrates the results.
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the through...
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ISBN:
(纸本)0780393333
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.
The coarse-grained reconfigurable design paradigm provides, in a wide scope of design cases, effective support for adaptability, as required in modern embedded systems. The Reconfigurable Platform Composer Tool (RPCT)...
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ISBN:
(纸本)9781509033614
The coarse-grained reconfigurable design paradigm provides, in a wide scope of design cases, effective support for adaptability, as required in modern embedded systems. The Reconfigurable Platform Composer Tool (RPCT) project and its main outcome, the Multi-Dataflow Composer, aim at reducing the effort related with the design, mapping, optimization and prototyping of coarse-grained reconfigurable systems.
A multiplier-free baseband filter is proposed for the low power VLSI implementation in a Code Division Multiple Access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter stru...
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ISBN:
(纸本)0780377958
A multiplier-free baseband filter is proposed for the low power VLSI implementation in a Code Division Multiple Access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter structure involving a pair of even and odd length FIR filter with same bandedges. It is shown by means of example that the new structure not only achieves 45.8% savings in the number of multipliers, but also reduces the word length requirement for the coefficients of an IS-95 CDMA baseband filter. The VLSI implementation shows that the new structure reduces both the chip area and power consumption considerably compared with the direct-form implementation.
Bandwidth to off-chip memory is a scarce resource in complex systems-on-Chip for embedded media processing. We apply embedded compression for bandwidth-hungry image processing functions in order to alleviate this band...
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ISBN:
(纸本)9781424403820
Bandwidth to off-chip memory is a scarce resource in complex systems-on-Chip for embedded media processing. We apply embedded compression for bandwidth-hungry image processing functions in order to alleviate this bandwidth bottleneck. In our solution embedded compression is implemented as part of the System-on-Chip infrastructure, fully transparent for the hardware and software image processing components. Hence it can be applied without requiring changes to these components. We present the compression algorithm and demonstrate that we achieve significant bandwidth reductions (20% - 40%) for image data at acceptable cost (approximately 1 mm(2) in 90 nm CMOS) while preserving high image quality.
Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be desc...
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ISBN:
(纸本)0780338065
Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be described to demonstrate how to overcome this gap. A more radical solution will then be described which no longer defines programming as a procedure that operates on data, but as a specification of data sets that require transformations. While this can be emulated on top of the CSP model, more efficient hardware implementations are possible. The author speculates that this could result in architectures that are hard real-time and optimised by design.
Power and thermal characteristics have emerged as first-order design goals for all types of semiconductors, including embedded signal and information processingsystems. This paper surveys the basic physical principle...
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ISBN:
(纸本)9781509033614
Power and thermal characteristics have emerged as first-order design goals for all types of semiconductors, including embedded signal and information processingsystems. This paper surveys the basic physical principles of power and thermal behavior and argues that statistical models, such as Markov decision processes, are well-suited to the management of power and thermal behavior at both design time and run time.
In this paper we propose to perform a complete error analysis of a fixed-point implementation of any linear system described by data-flow graph. The system is translated to a matrix-based internal representation that ...
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ISBN:
(纸本)9781538604465
In this paper we propose to perform a complete error analysis of a fixed-point implementation of any linear system described by data-flow graph. The system is translated to a matrix-based internal representation that is used to determine the analytical errors-to-output relationship. The error induced by the finite precision arithmetic (for each sum-of-product) of the implementation propagates through the system and perturbs the output. The output error is then analysed with three different point of view: classical statistical approach (errors modeled as noises), worst-case approach (errors modeled as intervals) and probability density function. These three approaches allow determining the output error due to the finite precision with respect to its probability to occur and give the designer a complete output error analysis. Finally, our methodology is illustrated with numerical examples.
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