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检索条件"任意字段=IEEE Workshop on Signal Processing Systems Design and Implementation"
10802 条 记 录,以下是181-190 订阅
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NEW VLSI SYSTOLIC ARRAY design FOR REAL-TIME DIGITAL signal-processing
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ieee TRANSACTIONS ON CIRCUITS AND systems 1986年 第6期33卷 673-676页
作者: LIN, H School of Engineering Technology South Carolina State College Orangeburg SC USA
The well-known advantages of pipelines systolic array architecture is applied for implementation of a second-order recursive digital filter. The proposed structure achieves five-fold increase in system throughput over... 详细信息
来源: 评论
implementation of the 2D DCT using a Xilinx XC6264 FPGA
Implementation of the 2D DCT using a Xilinx XC6264 FPGA
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1997 ieee workshop on signal processing systems (SiPS 97) - design and implementation
作者: Trainor, DW Heron, JP Woods, RF Integrated Silicon Systems Ltd Belfast United Kingdom
This paper presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs fo... 详细信息
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Optimized software synthesis for digital signal processing algorithms: An evolutionary approach
Optimized software synthesis for digital signal processing a...
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1998 ieee workshop on signal processing systems - design and implementation (SiPS'98)
作者: Teich, J Zitzler, E Bhattacharyya, SS Swiss Fed Inst Technol Inst TIK CH-8092 Zurich Switzerland
Based on the model of synchronous data flow (SDF) [13], so called single appearance schedules are known to provide memory-optimal schedules. Among these, the problem of buffer memory optimization is treated: (I) An Ev... 详细信息
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Power and Thermal Modeling for Communication systems
Power and Thermal Modeling for Communication Systems
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ieee International workshop on signal processing systems (SiPS)
作者: Wolf, Marilyn Bhattacharyya, Shuvra Florence, Jacques Sapio, Adrian E. Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA
Power and thermal characteristics have emerged as first-order design goals for all types of semiconductors, including embedded signal and information processing systems. This paper surveys the basic physical principle... 详细信息
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Taurus: A multiprocessor DSP prototyping environment
Taurus: A multiprocessor DSP prototyping environment
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1997 ieee workshop on signal processing systems (SiPS 97) - design and implementation
作者: Razaz, M Marlow, K Univ of East Anglia Norwich United Kingdom
Many signal processing applications are computationally intensive, and can not be implemented on a single processor. The concept of automatic parallel implementation of such applications on multiple connected processo... 详细信息
来源: 评论
A mixed QOS SDRAM controller for FPGA-based high-end image processing
A mixed QOS SDRAM controller for FPGA-based high-end image p...
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ieee workshop on signal processing systems
作者: Heithecker, S Lucas, AD Ernst, R Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Commun Network Engn D-3300 Braunschweig Germany
High-end video and multimedia processing applications today require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, accessing SDRAM is a complex task, esp... 详细信息
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Scheduling and allocation of single-chip multiprocessors for multimedia
Scheduling and allocation of single-chip multiprocessors for...
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1997 ieee workshop on signal processing systems (SiPS 97) - design and implementation
作者: Li, YB Wolf, W Princeton Univ Princeton United States
Software synthesis is an increasingly important problem in the design of digital signal processing systems, since multimedia systems in particular are increasingly implemented using a combination of programmable and h... 详细信息
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Hardware efficient base-4 systolic architecture for computing the discrete Fourier transform  16
Hardware efficient base-4 systolic architecture for computin...
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ieee workshop on signal processing systems (SIPS 02)
作者: Nash, JG Centar United States
A systolic architecture is described for computing the I-D discrete Fourier transform, which provides a significant reduction in array area by reducing the number of complex multipliers compared to previous systolic a... 详细信息
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OBTAINING SCHEDULES FOR DIGITAL-systems
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ieee TRANSACTIONS ON signal processing 1991年 第10期39卷 2296-2316页
作者: JAGADISH, HV KAILATH, T STANFORD UNIV ELECT ENGNSTANFORDCA 94305
When designing digital hardware for a given signal processing algorithm, one must ensure that signals arrive at the appropriate points of the implementation at the right times, so that they are operated upon as specif... 详细信息
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Exploit multiple-domain sparseness for HSDPA (Chip level equalization in SDR: Algorithm and DSP implementation
Exploit multiple-domain sparseness for HSDPA (Chip level equ...
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ieee workshop on signal processing systems design and implementation
作者: Li, Min Bougard, Bruno Catthoor, Francky IMEC VZW Kapeldreef 75 B-3001 Louvain Belgium
Chip level equalization has been proved as one of the key enabling technologies for HSDPA (High Speed Downlink Packet Access) receiver. Although many complicated algorithms (Kalman, etc.) have been reported to have gr... 详细信息
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