While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative bra...
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While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processingsystems. Within this context, neuromorphic engineering represents a paradigm shift in computing based on the implementation of spiking neural network architectures in which processing and memory are tightly colocated. In this article, we provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized and comparing design approaches that focus on replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down). First, we present the analog, mixed-signal, and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation, and novel devices. Then, we highlight the key tradeoffs for each of the bottom-up and top-down design approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic systems over conventional machine-learning accelerators in edge computing applications and outline the key ingredients for a framework toward neuromorphic intelligence.
Ambient backscatter communication (AmBC) is becoming increasingly popular as a green Internet-of-things technology by enabling ultra-low-power data exchanges among simple tags. The bit-error-rate (BER) performance of ...
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Ambient backscatter communication (AmBC) is becoming increasingly popular as a green Internet-of-things technology by enabling ultra-low-power data exchanges among simple tags. The bit-error-rate (BER) performance of the AmBC receivers is hampered by the low signal-to-interference-plus-noise ratio (SINR), which limits either the range or the data rate that can be supported by these systems. Among the alternatives, the solutions provided by a multiantenna receiver enable several practical methods to improve the SINR using array signalprocessing. In this paper, the optimum multiantenna AmBC receiver for any binary modulated tag signal is presented. Two receivers are derived from the maximum-a-posterior probability criterion for deterministic-unknown and for Gaussian distributed ambient signals. The closed-form cumulative distribution functions are derived for both of the receivers for performance evaluation purposes. It is discussed that these two receivers are equivalent under practical conditions, and the optimum receiver is a generalization of the multiantenna receivers available in the literature. Several implementation details are discussed, and numerical evaluation is provided to validate the development. Therefore, the presented receiver accommodates different tag modulations and achieves the best possible BER performance, which opens up new application possibilities by improving AmBC system flexibility.
This letter analyzes the optimal transmission period to maximize the time-averaged received power using a distributed microwave power transfer (DMPT) system. DMPT requires periodic phase and frequency synchronization....
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This letter analyzes the optimal transmission period to maximize the time-averaged received power using a distributed microwave power transfer (DMPT) system. DMPT requires periodic phase and frequency synchronization. The received power is maximized immediately after synchronization because the received signals from the transmitters are coherent. However, the received power gradually degrades owing to the phase drift caused by the frequency offset of the phase-locked loop (PLL) on the transmitters. Therefore, if the power transmission period is considerably long, the time-averaged received power decreases. To design the synchronization interval, we formulated the expected value of the time-averaged received power. The expected value assists in selecting PLL elements and estimating the received power before hardware implementation of the transmitters, thus enabling the rapid design of DMPT systems.
In this paper, we propose the decentralized likelihood ascent search (DLAS)-aided detection for the distributed large-scale multiple-input multiple-output (MIMO) systems to achieve more remarkable performance gains. W...
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In this paper, we propose the decentralized likelihood ascent search (DLAS)-aided detection for the distributed large-scale multiple-input multiple-output (MIMO) systems to achieve more remarkable performance gains. With the help of DLAS, traditional distributed iterative methods are able to achieve better performance than the linear detection schemes such as ZF and MMSE. According to analysis, we derive the equivalent noise and the post-processing SNR for DLAS. More importantly, based on them, we demonstrate that the proposed DLAS-aided detection achieves the full received diversity. To further facilitate its implementation in practice, we design the decentralized effective ring (DER) architecture with significantly reduced bandwidth requirement and better parallel computation. Finally, simulation results demonstrate that the proposed DLAS-aided detection attains the same received diversity as ML detection while surpassing state-of-the-art decentralized schemes in terms of BER performance, with reduced complexity and bandwidth costs.
A novel down-sampling filter named moving accumulative sign filter (MASF) is proposed for low-power down-sampling of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages th...
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A novel down-sampling filter named moving accumulative sign filter (MASF) is proposed for low-power down-sampling of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages than state-of-the-art cascaded-integrator-comb (CIC) filter, especially in the area of low-power design. The theory of MASF is proposed and introduced comprehensively, including the algorithm model, transfer function, and frequency response characteristics. The pipeline voting architecture is applied to the implementation of the MASF to improve the speed of data processing, which simplifies the circuit structure and reduce the power consumption. The MASF circuits of general application based on pipeline voting are designed for binary and ternary signals only using D flip-flop and logic gates. The area and power consumption of MASF are reduced by 86% and 88% compared with CIC filter under the same conditions on FPGA. What's more, a hardware-friendly pooling algorithm named polar-pooling is proposed based on MASF for binary and ternary feature maps, which greatly reduces the time and space complexity of pooling. Compared with max-pooling and average-pooling, the processing time of polar-pooling is reduced by more than 75% for a $200\times 200$ binary image. The two-stage MASF circuit for ternary signalprocessing is implemented at 40-nm CMOS process, compared with state-of-the-arts cascade-of-integrators filter which cascading two integrators, the normalized power consumption of proposed two-stage MASF circuit has 67% reduction and the area has 75% reduction.
This paper presents an Application-Specific Integrated Circuit (ASIC) implementation suitable for healthcare applications that employ RISC-V as a digital processing unit and sensor interfacing circuits. systems on Chi...
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This paper tackles the problem of precoding and decoding matrices design for a time-division duplexing (TDD) massive MIMO system to support Ns independent data streams. The optimal design requires estimating the top-N...
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According to literature, designers spend up to 30% of the design time on optimizing data representations in signalprocessing architectures [13]. Reference implementations, mostly in high-level software languages, cho...
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ISBN:
(纸本)9798400700453
According to literature, designers spend up to 30% of the design time on optimizing data representations in signalprocessing architectures [13]. Reference implementations, mostly in high-level software languages, choose floating point representation for mathematical calculations, which are too resource-intensive for FPGA implementations in many cases. The task of conversion to bit-width-optimized fixed point representations is tedious and therefore warrants automation. Usually some analytical or simulation-based approach is used for this, but past works usually overcomplicate their mode of operation and are therefore not commonplace in FPGA design. In this work, it is shown that a simulation-based approach can be both fast, given modern hardware, as well as simple enough to be integrated into a modern design flow. Using a real-world design from a complex power quality measurement algorithm, this is demonstrated and evaluated. Our implementation was able to reach much better results by reducing the resource utilization by approximately 80%, compared to the bit-widths proposed by a field expert while retaining the accuracy needed for the target application.
This paper presents the design and implementation of a compact frequency-and radiation pattern reconfigurable patch antenna integrated with 4 PIN diodes on FR - 4(ϵ=4.4 and height =1.6 mm) substrate measuring 30 mm &#...
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AbsiTact-Group operations determine how efficientiy elliptic curve cryptography (ECC) can operate. In Ibis study, we propose efcient and optimized potut addition (PA) and point doubling (PD) algorithms and hardware ar...
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