This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When reali...
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ISBN:
(纸本)0780393333
This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4ms to perform lossless image compression on a 128x128 16-bit discrete wavelet transformed image. It uses 392 slices, similar to 15KB of RAM memory and dissipates just 8.2mW/MHz.
In the near future, Global Positioning System (GPS) data will be used in a wide variety of portable, mobile electronic devices. Shrinking feature sizes, combined with the need for low-power, lightweight components, wi...
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ISBN:
(纸本)0780349970
In the near future, Global Positioning System (GPS) data will be used in a wide variety of portable, mobile electronic devices. Shrinking feature sizes, combined with the need for low-power, lightweight components, will drive an entire GPS receiver onto a single, mixed-signal die. A major design issue in mixed-signalsystems is the effect of digital switching noise coupled to sensitive analog circuits through the substrate. A method is proposed for minimizing this effect by partitioning digital and analog processing into separate time blocks. The resulting trade-off between lost signal and increased energy consumption is explored. In particular, a GPS synchronizer design is analyzed with respect to modifications that can be made to increase performance, while minimizing any associated energy penalty.
The emerging of mobile multimedia terminals has given rise to growing demands for the power-efficient and scalable image transmission. Visual Texture Coding (VTC) has attracted increasing attention due to its scalabil...
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ISBN:
(纸本)0780377958
The emerging of mobile multimedia terminals has given rise to growing demands for the power-efficient and scalable image transmission. Visual Texture Coding (VTC) has attracted increasing attention due to its scalability when transmitting still images. Nowadays, the implementation of such VTC decoders has not yet considered the need of energy performance trade-offs at the system-level. We have applied systematic system-level design techniques to analyze the VTC decoder and explore its timing-energy trade-off space by using our concurrent task scheduling exploration techniques. The approach presented in this paper allows a system designer to select the optimal heterogeneous platform configuration for a given speed of the VTC decoder while minimizing the global energy consumption.
We present a systolic algorithm for performing interpolation, a computationally intensive kernel found in algebraic soft-decoding of Reed-Solomon codes. We reformulate the interpolation algorithm, resulting in the sys...
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ISBN:
(纸本)0780377958
We present a systolic algorithm for performing interpolation, a computationally intensive kernel found in algebraic soft-decoding of Reed-Solomon codes. We reformulate the interpolation algorithm, resulting in the systolic interpolation algorithm, which can compute a reduced number of candidate polynomial coefficients. Using the dependence graph of the algorithm, we realize a low-latency interpolation architecture and a high-throughput interpolation architecture. These architectures are compared against previously proposed architectures for a RS soft-decoder. We derive expressions for the latency of the systolic implementations and show that, for a reasonable hardware constraint, the low-latency systolic implementation reduces latency by 34% for a [255, 239] RS code. For the same code and hardware constraints, the high-throughput implementation with a block pipelining depth of 5, increases throughput by 68%. In addition, the critical path of both the low-latency and the high-throughput implementation is smaller than that of previously proposed architectures.
This paper presents an ASIC implementation of a WCDMA Rake receiver. The implementation is based on a FlexRake architecture that shares resources between multipath components and uses parallelism for multiple code cha...
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ISBN:
(纸本)0780375874
This paper presents an ASIC implementation of a WCDMA Rake receiver. The implementation is based on a FlexRake architecture that shares resources between multipath components and uses parallelism for multiple code channels. This approach facilitates the multipath allocation and improves the receiver modularity. The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells. Synthesis for 0.35 mum technology resulted in 0.894 mm(2) area and 3.63 mW power consumption at 2.7 V.
Over the last few decades, the use of Sigma-Delta (Sigma-Delta) modulators, has moved into mainstream applications in signalprocessing such as A/D, D/A, and communication. Sigma-Delta modulators produce a single, or ...
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ISBN:
(纸本)0780377958
Over the last few decades, the use of Sigma-Delta (Sigma-Delta) modulators, has moved into mainstream applications in signalprocessing such as A/D, D/A, and communication. Sigma-Delta modulators produce a single, or few bits output making them suitable for realization in VLSI circuits. For improved signal-to-quantization-noise ratio, higher order modulators, such as multi-loop and multi-stage architecture, are commonly used. The quantization noise behavior of these higher order modulators is well understood. Based on these quantization noise characteristics, various demodulator architectures, such as optimal FIR filter, Sinc filter, and Laguerre filter are reported in the literature. In this paper, an efficient FPGA (Field Programmable Gate Array) implementation of a Kalman recursive low-pass filter suitable for application in Sigma-Delta demodulation is reported. FPGA Synthesis results, as well as filter performance, as compared to previous designs for Sinc filter and Laguerre filter, is given.
Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of precalculated partial products. A method is proposed for reducing switching ac...
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ISBN:
(纸本)0780349970
Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of precalculated partial products. A method is proposed for reducing switching activity, and hence power dissipation, in distributed arithmetic systems used for processing signed data. By performing a recoding of the two's complement inputs into a nonredundant signed-digit representation, the table lookups and accompanying accumulations corresponding to the sign extensions in the higher-order bit positions can be reduced.
Precoding based on channel state information (CSI) can help improve the performance of orthogonal space-time block codes (OSTBCs). Optimum precoders require a fairly detailed description of the channel singular vector...
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ISBN:
(纸本)9781424403820
Precoding based on channel state information (CSI) can help improve the performance of orthogonal space-time block codes (OSTBCs). Optimum precoders require a fairly detailed description of the channel singular vectors motivating the use of limited feedback communications to send some quantized form of the precoder to the transmitter. To this end, the singular value decomposition (SVD) is the fundamental step in extracting the singular vectors of the channel. In this paper we revisit a limited feedback technique based on the quantization of the dominant right singular vector of the channel matrix. Lifting the assumption of perfect channel estimation at the receiver, we investigate channels affected by Gaussian noise, fine of sight component, and phase uncertainty. We also assume a more general channel model that incorporates channel correlations. Our simulations show that the quantized nature of the precoders provides the system with resiliency to such impairments.
Bio-inspired machine learning algorithms, such as Convolutional Neural Networks (CNNs), offer interesting solutions to complex real-life problems that cannot be simply modeled. Applications involving image recognition...
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ISBN:
(纸本)9781728180991
Bio-inspired machine learning algorithms, such as Convolutional Neural Networks (CNNs), offer interesting solutions to complex real-life problems that cannot be simply modeled. Applications involving image recognition and object detection can greatly benefit from these approaches. Furthermore, their intrinsic and regular parallel structure offer opportunities regarding hardware acceleration. However, moving compute and memory-intensive CNNs to embedded systems while maintaining high energy-efficiency remains challenging. This paper presents the first step of a generic framework targeting the characterization of neural network algorithms to improve their implementation on embedded systems. The presented approach aims at reducing the gap between the fast-changing landscape of applications based on artificial intelligence and the hardware targets. The framework computes different metrics from neural network descriptions (such as computation and memory needs or data locality and reuse) to derive appropriate implementation strategies, or configurations of target architectures. Based on the outputs of the framework, new neural networks topologies can be quickly studied to reduce time-to-market of new systems.
Under multipath conditions, standard Video Intermediate Frequency (VIF) detectors generate a local oscillator phase error and consequently produce a dispersed non-ideal detected video signal due to the presence of add...
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ISBN:
(纸本)0780338065
Under multipath conditions, standard Video Intermediate Frequency (VIF) detectors generate a local oscillator phase error and consequently produce a dispersed non-ideal detected video signal due to the presence of additional IF carriers. The dispersed video causes problems when attempting to identify and remove the multipath interference, or ghosts, by the use of Digital signalprocessing and digital filtering. A digital phase lock system is presented which derives the correct phase for synchronous detection in the presence of multipath by using correlation information that has already been calculated as part of the deghosting process. As a result, the video deghoster system is made simpler, faster and more economical.
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