Dataflow modeling offers a myriad of tools in designing and optimizing signalprocessingsystems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with functiona...
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ISBN:
(纸本)9781479965885
Dataflow modeling offers a myriad of tools in designing and optimizing signalprocessingsystems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with functionality and different performance metrics. However, a disparity in the specification of dataflow properties and the final implementation can lead to incorrect behavior that is difficult to detect. This motivates the problem of ensuring consistency between dataflow properties that are declared or otherwise assumed as part of dataflow-based application models and the dataflow behavior that is exhibited by implementations that are derived from the models. In this paper, we address this problem by introducing a novel dataflow validation framework (DVF) that is able to identify disparities between an application's formal dataflow representation and its implementation. We demonstrate the utility of our DVF through design and implementation case studies involving an automatic speech recognition application, and a JPEG encoder.
In this paper we shall present an NDA (Non Data Aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (Additive White Gaussian Noise). It shall be shown that the detector allows the car...
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ISBN:
(纸本)9781424403820
In this paper we shall present an NDA (Non Data Aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (Additive White Gaussian Noise). It shall be shown that the detector allows the carrier synchronization PLL (Phase Locked Loop) to achieve optimal performance during both the acquisition and tracking operation modes. The conditions necessary for this optimality to be achieved will be discussed, and it shall be shown that they are quite reasonable and allow the proposed detector to be implemented in many contemporary M-PSK receivers. The optimal behaviour of the PLL will be shown to hold regardless of the SNR (signal-to-Noise Ratio) and of the AGC (Automatic Gain Control) circuit behaviour. Moreover, the proposed detector has a simple fixed-point structure that can be feasibly implemented using few hardware resources within contemporary FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits). Finally, operation of the proposed detector under frequency-flat slow signal fading conditions is also discussed.
An efficient technique for hierarchical image coding is proposed, which divides an image into its multiple resolution versions with minimum hardware cost. Since the proposed technique uses discrete cosine transform (D...
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ISBN:
(纸本)0780377958
An efficient technique for hierarchical image coding is proposed, which divides an image into its multiple resolution versions with minimum hardware cost. Since the proposed technique uses discrete cosine transform (DCT) over each frequency band data, obtained directly from DCT domain by multiplying pre-calculated matrices, compatibility can be preserved easily with DCT-based image/video standards. First, we present the 1-D case, followed by an extension to the 2-D case. The proposed coder is observed to result in significant reduction of memory and computational complexity requirement with higher peak signal to noise ratio (PSNR), when compared with traditional hierarchical image coding method.
Software Defined Radio(SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generati...
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ISBN:
(纸本)9781424403820
Software Defined Radio(SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include Turbo coding because of its superior performance. However, Turbo decoding is computationally intensive, and its low, power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of Turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate Turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of Turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2Mbps decoding throughput.
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fas...
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ISBN:
(纸本)9781728180991
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1/2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.
Currently, information security is an important issue in our information society and technology. In this paper, we propose two efficient architectures for processor of 128-bit block cipher SEED using 32-bit data bus. ...
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ISBN:
(纸本)0780377958
Currently, information security is an important issue in our information society and technology. In this paper, we propose two efficient architectures for processor of 128-bit block cipher SEED using 32-bit data bus. We compare the proposed architectures with the conventional SEED processor. The proposed SEED processors improve speed and reduce the hardware resources using only one G-function in the F-function and the key scheduler of SEED. The operation of the proposed methods has been verified with functional simulation, synthesis and tested on board. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.
Mobile multimedia computing and communication target several challenging goals for providing better quality of service and extending the mission time of battery powered handheld devices. Therefore, design of low-energ...
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ISBN:
(纸本)0780385047
Mobile multimedia computing and communication target several challenging goals for providing better quality of service and extending the mission time of battery powered handheld devices. Therefore, design of low-energy computing and communication systems has become important. In this paper, a joint control methodology of error protection capability and modulation strategy is presented to minimize the energy dissipation of a given communication. The communication energy includes the energy consumption of the underlying digital (channel encoder/decoder) and analog blocks including the RF amplifier. The energy dissipation of these blocks are determined by the system configuration parameters like channel coding rate, modulation order, transmission power and transmission duration. Simulation was performed on various channel qualities using Nakagami channel model. The simulation results show that the jointly controlled communication system enhances energy efficiency. When Nakagami fading figure is 6, 25% of energy can be saved on an average from QPSK system with channel coding rate of 0.5. The configuration of the system should be determined considering channel quality (fading and path loss).
Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, ...
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ISBN:
(纸本)9781424403820
Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, due to the trend of system-on-chip (SOC), rapid prototyping and intelligent soft IP designs are important design methodologies. In this paper, we design and implement a variable-length FFT processor to cover different applications of OFDM systems. We propose an efficient design flow which makes re-designing an FFT processor rapid and easy. We adopt cached-memory structure in the FFT processor for low-power consumption issue. Besides, we employ block-floating-point (BFP) arithmetic to acquire high signal to quantization noise ratio (SQNR). Finally, we implement this processor with TSMCO.18 mu m 1P6M CMOS technology. The simulation results show that the chip can perform 64 similar to 2048-point FFT operations at 75 MHz which meet the speed requirements of most OFDM standards such as WLAN, ADSL, VDSL (256 similar to 2048), DAB, and DVB (2k mode).
In this work, a software package and the associate teaching plan are provided for computationally efficient analysis and simulation of nonlinear systems. This MATLAB based tool can be used during senior undergraduates...
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ISBN:
(纸本)0780384342
In this work, a software package and the associate teaching plan are provided for computationally efficient analysis and simulation of nonlinear systems. This MATLAB based tool can be used during senior undergraduates and graduate level. The students can use this software for system level design and simulation of the effect of nonlinearity and noise in communication transceivers or fast implementation of Volterra filters for a class of sparse vectors.
In this paper, we investigate a acoustic echo cancellation method using blind source separation technique. In the hands-free mobile system, the large acoustic noise picked up by the microphone is mixed with the echo, ...
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ISBN:
(纸本)0780377958
In this paper, we investigate a acoustic echo cancellation method using blind source separation technique. In the hands-free mobile system, the large acoustic noise picked up by the microphone is mixed with the echo, then the echo cancellation system shows poor performance. We used blind source separation algorithm to control the acoustic noise which has to be suppressed. Blind source separation algorithm separate original echo signal from observation signal which is mixed by acoustic noise. The separated echo signal applied to the reference signal of the adaptive filter, this approach bring good performance of adaptive algorithm for echo cancellation. Computer simulation results show the efficiency of the suggested method.
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