This paper demonstrates a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding b...
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ISBN:
(纸本)9781479965885
This paper demonstrates a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates and serial processing. Clockless decoding increases the throughput of the decoder by eliminating the requirement for node signals to be synchronized after each decoding cycle. The design is implemented on an ALTERA Stratix IV EP4SGX230 FPGA and the frame error rate (FER), throughput, and power performance are presented for (96,48) and (204,102) LDPC decoders.
This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signalprocessing algorithms. We present our view of a framework that combines...
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ISBN:
(纸本)9781424403820
This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signalprocessing algorithms. We present our view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance. We use our framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. Our framework is well suited for designers with a range of signalprocessing and hardware expertise. Our framework generates the dedicated IP cores and estimates the performance such as area, critical path delay, and latency within seconds. Parts of our framework also compare different hardware designs for various digital signalprocessing (DSP) algorithms and allows the designer to make architectural decisions earlier in the hardware design process. We use a GUI-based framework invoked from MATLAB to automatically build and analyze the hardware designs. Our framework generates efficient hardware designs described in SystemC and Verilog code, along with the performance metrics for each architecture. We illustrate the use of our framework by exploring and analyzing architectural variations of two case studies: finite impulse response (FIR) filters and adaptive channel equalizers.
Multiple-input multiple-output (MIMO) is an existing technique that can significantly increase throughput of the system by employing multiple antennas at the transmitter and the receiver. Realizing maximum benefit fro...
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ISBN:
(纸本)9781424443345
Multiple-input multiple-output (MIMO) is an existing technique that can significantly increase throughput of the system by employing multiple antennas at the transmitter and the receiver. Realizing maximum benefit from this technique requires computationally intensive detectors which poses significant challenges to receiver design. Furthermore, a flexible detector or multiple detectors are needed to handle different configurations. Graphical Processor Unit (GPU), a highly parallel commodity programmable co-processor, can deliver extremely high computation throughput and is well suited for signalprocessing applications. However, careful architecture aware design is needed to leverage performance offered by GPU. We show we can achieve good performance while maintaining flexibility by employing an optimized trellis-based MIMO detector on GPU.
The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. The energy limitations ...
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ISBN:
(纸本)0780393333
The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. The energy limitations of mobile appliances create the demand for low-power implementations. We propose a custom high-performance MPEG-4 video encoder. The fully dedicated video pipeline is realized using a systematic design approach and exploits the inherent functional parallelism of the compression algorithm. Memory optimizations and algorithmic optimizations combined at the high-level and their effect on the power-efficiency is demonstrated. The resulting MPEG-4 video encoder contains a tailored memory hierarchy;uses burst oriented accesses to external memory and supports real-time processing of 30 4CIF frames per second while only consuming 71 mW in a 180 mn, 1.62V UMC technology.
Hybrid Filter Banks (HFB) are the suitable candidate for implementing wide-band, high-frequency A/D parallel converters. This paper proposes a modified HFB configuration called two-stage structure to overcome the alia...
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ISBN:
(纸本)0780393333
Hybrid Filter Banks (HFB) are the suitable candidate for implementing wide-band, high-frequency A/D parallel converters. This paper proposes a modified HFB configuration called two-stage structure to overcome the aliasing constraints. This structure yields much better performance in terms of aliasing, or equally a higher possible resolution than the original one. Moreover, this two-stage structure can provide the performance of the original one with approximately only half the number of coefficients in the FIR Synthesis filters. Results will be shown in the realistic case when the analog analysis filters are easy-to-implement RLC (or RC) circuits.
The problem of source separation of instantaneous mixtures has been addressed thoroughly in literature in the past. The assumption of statistical independence between the source signals, led to the introduction of Ind...
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ISBN:
(纸本)0780393333
The problem of source separation of instantaneous mixtures has been addressed thoroughly in literature in the past. The assumption of statistical independence between the source signals, led to the introduction of Independent Component Analysis (ICA). A number of methods, based on the ICA framework, can identify nonGaussian sources in instantaneous mixtures with robust convergence and performance. However, in several biomedical applications, there is a need to identify and separate signals that, apart from being nonGaussian, are not symmetric. In this article, the authors present a method for blind identification and separation of skewed (non-symmetric) signals in a linear instantaneous mixture.
Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent appr...
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ISBN:
(纸本)0780393333
Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VRDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VRDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations.
Future terminals for CDMA will have to employ multiuser detection to implement high data rate modes such as HSDPA in the UTRA/3GPP standard. Therefore efficient and flexible detection algorithms are needed. In [1] we ...
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ISBN:
(纸本)0780393333
Future terminals for CDMA will have to employ multiuser detection to implement high data rate modes such as HSDPA in the UTRA/3GPP standard. Therefore efficient and flexible detection algorithms are needed. In [1] we have already shown an approach of such an equalizer for single user detection. The principle algorithm of this equalizer has now been extended to a multiuser detector, which can make use of the same Cordic based platform as the original equalizer. The paper shows that our approach has got a significant performance increase in comparison to a standard Rake based equalizer, whereas the computational complexity remains roughly the same.
In this work, a software package and the associate teaching plan are provided for computationally efficient analysis and simulation of nonlinear systems. This MATLAB based tool can be used during senior undergraduates...
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ISBN:
(纸本)0780384342
In this work, a software package and the associate teaching plan are provided for computationally efficient analysis and simulation of nonlinear systems. This MATLAB based tool can be used during senior undergraduates and graduate level. The students can use this software for system level design and simulation of the effect of nonlinearity and noise in communication transceivers or fast implementation of Volterra filters for a class of sparse vectors.
We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. ...
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We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signalprocessing algorithms are efficiently implemented
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