This paper focuses on estimating the evoked potentials (EP) signal recorded from human scalp that occurs in response to an externally applied stimulus, A Fourier series model for time-varying EP is chosen here. The mo...
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ISBN:
(纸本)0780364880
This paper focuses on estimating the evoked potentials (EP) signal recorded from human scalp that occurs in response to an externally applied stimulus, A Fourier series model for time-varying EP is chosen here. The model parameters are estimated by an RLS adaptive procedure, enabling the estimator efficiency track clinically significant alteration in the EP.
Although a number of diverse edge detection techniques can be found in many image processing publications, there is no single detection method that performs well in every possible image context. Information that could...
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ISBN:
(纸本)0780393333
Although a number of diverse edge detection techniques can be found in many image processing publications, there is no single detection method that performs well in every possible image context. Information that could be missed by one detector may be captured by another. The purpose of this paper is to describe a new framework which allows us to quantitatively combine the methods of different edge detection operators in order to yield improved results for edge detection in an image. The so called Receiver Operating Characteristics (ROC) analysis is employed in a novel fashion to form an optimum edge map that matches the outcomes of a preselected set of edge detectors. The results of applying the above ROC analysis technique are demonstrated and compared with individual edge detection methods.
Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, ...
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ISBN:
(纸本)9781424403820
Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, due to the trend of system-on-chip (SOC), rapid prototyping and intelligent soft IP designs are important design methodologies. In this paper, we design and implement a variable-length FFT processor to cover different applications of OFDM systems. We propose an efficient design flow which makes re-designing an FFT processor rapid and easy. We adopt cached-memory structure in the FFT processor for low-power consumption issue. Besides, we employ block-floating-point (BFP) arithmetic to acquire high signal to quantization noise ratio (SQNR). Finally, we implement this processor with TSMCO.18 mu m 1P6M CMOS technology. The simulation results show that the chip can perform 64 similar to 2048-point FFT operations at 75 MHz which meet the speed requirements of most OFDM standards such as WLAN, ADSL, VDSL (256 similar to 2048), DAB, and DVB (2k mode).
FPGA-based DSP generally has two aspects: processing pipelines and finite state machine (FSM) controllers. implementation of these components are typically one of the more challenging parts of the project that often t...
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ISBN:
(纸本)9781538663189
FPGA-based DSP generally has two aspects: processing pipelines and finite state machine (FSM) controllers. implementation of these components are typically one of the more challenging parts of the project that often takes a significant portion of development time. Furthermore, it is a part of the code that may be the limiting factor in system performance. The ALCHA language is a new programming language for coding FPGA firmware that is currently under development. ALCHA focuses on providing a variety of powerful features that will improve developer productivity. This paper presents ALCHA features that aim to support the two DSP features mentioned above. Pipelining is facilitated by letting the developer write code in terms of real-world units, such as voltage, metres and radians. The implementation of FSM controllers is supported by using a structured procedural programming model to express algorithm flow. The programming model has been designed with object-orientation in mind so that the ALCHA user can make use of polymorphism and other abstraction mechanisms.
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fas...
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ISBN:
(纸本)9781728180991
Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1/2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.
There are many applications within digital signalprocessing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval ...
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ISBN:
(纸本)9781424403820
There are many applications within digital signalprocessing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors ate needed to implement interval arithmetic. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division traditionally is not implemented on digital signal processors unless computed with a shift operation. In this design, division by shifting is implemented. The ALU is designed to have maximum throughput while minimizing area.
Digital signal-processing-based coherent optical communication systems are widely viewed as the most promising next-generation long-haul transport systems. One of the biggest challenges in building these systems is th...
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Digital signal-processing-based coherent optical communication systems are widely viewed as the most promising next-generation long-haul transport systems. One of the biggest challenges in building these systems is the implementation of signal processors that are able to deal with signaling rates of a few tens of giga-samples per second. In this paper, we discuss implementation options and design considerations with respect to hardware realization and DSP implementation.
In this paper we present a novel method for gesture video decomposition based on the depicted content. From the initial content the key-frames are extracted and the neighboring frames are assigned to key-frames of sim...
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ISBN:
(纸本)0780393333
In this paper we present a novel method for gesture video decomposition based on the depicted content. From the initial content the key-frames are extracted and the neighboring frames are assigned to key-frames of similar content. The resulting frame groups are decomposed to binary trees, based on the energy of the depicted gestures. In case of reduced bandwidth we keep the original timeline but we send only a dynamically adapted video summary. The respective frames are obtained by moving appropriately across the hierarchy layers of the constructed tree. The hierarchically structured video can be used for purposes such as efficient video browsing and transmission of dynamically generated summaries over low bandwidth networks, for communication or human-computer interface applications.
In this paper, a new soft output MIMO decoder based on the k-best search scheme and additional partial Euclidian distance (PED) update schemes is developed. The k-best framework facilitates a constant throughput imple...
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ISBN:
(纸本)9781467362382
In this paper, a new soft output MIMO decoder based on the k-best search scheme and additional partial Euclidian distance (PED) update schemes is developed. The k-best framework facilitates a constant throughput implementation and the PED update schemes help achieve a more accurate log-likelihood ratio (LLR) calculation. A LLR clamping technique is further adopted to enhance the BER performance when combining with the LDPC coding. Simulation results indicate the effectiveness of the proposed PED update schemes against previous works. Efficient architecture design is next developed capable of accomplishing one 4X4 MIMO signal vector detection every 4 clock cycles. In FPGA implementation, the maximum working frequency can be up to 121.3MHz and suggests a 720Mbps data rate for a 4X4 MIMO system using 64QAM modulation.
Hybrid video compression schemes store an entire image for predictive coding. Traditionally, this image is stored in the time domain needing almost 5 Mbit of memory for main-level image format. The amount of storage s...
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ISBN:
(纸本)0780349970
Hybrid video compression schemes store an entire image for predictive coding. Traditionally, this image is stored in the time domain needing almost 5 Mbit of memory for main-level image format. The amount of storage space can be reduced if the data is stored in the RLE-DCT domain, even using the available compression and buffer-control algorithm to guarantee a storage amount. We show that a hardware implementation is feasible and worthwhile in relation to traditional encoders. Motion estimation is performed by recursive blockmatching, at sub-pixel accuracy.
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