Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner's timing error detector...
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ISBN:
(纸本)9781424403820
Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner's timing error detector. The contribution of this paper is twofold. First, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. Second, some design rules are given to predict the behaviour of the loop if pipeline is used. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.
A pipelined architecture aids the efficient implementation of a Delayed LMS algorithm but requires a considerable processing delay. In this paper, an efficient method for determining the delays in the feedback loop of...
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ISBN:
(纸本)0780375874
A pipelined architecture aids the efficient implementation of a Delayed LMS algorithm but requires a considerable processing delay. In this paper, an efficient method for determining the delays in the feedback loop of DLMS filter is presented. This is used to design a series of Retimed Delayed LMS (RDLMS) architectures which allow a higher throughput rate and 66.7% reduction in the delays of previous designs. The resulting design also converges 5 times faster. Three architectures and three hardware shared versions have been designed and implemented using the Virtex-II FPGA. A speed of 182 Megasamples/s has been achieved.
Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implem...
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ISBN:
(纸本)0780375874
Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implementing conventional block-floating-point arithmetics. This paper describes an actual implementation of the DSP architecture on a field programmable gate array (FPGA) platform. Some signalprocessing quality evaluation results are also presented for two audio applications that are realized on the DSP architecture.
A common inaccuracy that is made when computing the capacity of digital channels, is to assume that the inputs and outputs of the channel are analog Gaussian random variables and then based upon that assumption, invok...
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ISBN:
(纸本)0780393333
A common inaccuracy that is made when computing the capacity of digital channels, is to assume that the inputs and outputs of the channel are analog Gaussian random variables and then based upon that assumption, invoke the Shannon capacity bound for an additive white Gaussian noise (AWGN) channel. In a channel utilizing a finite set of inputs and outputs, clearly the inputs and outputs are not Gaussian distributed and Shannon bound is not exact. In this paper we study the capacity of a block transmission AWGN channel with quantized inputs and outputs given the simultaneous constraints that the channel is frequency selective and there exists an average power constraint P at the transmitter. The channel is assumed known at the transmitter. In [13] we show supporting simulation results consequent upon the theoretical framework developed in this paper as well as the results obtained by applying the framework to a practical example.
SystemC is a new hardware design concept that enables the designer to perform early functional verification of developed hardware blocks by facilitating their integration with software in a unified platform. It provid...
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ISBN:
(纸本)0780393333
SystemC is a new hardware design concept that enables the designer to perform early functional verification of developed hardware blocks by facilitating their integration with software in a unified platform. It provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. In this paper, we propose a strategy that enables us to emulate a model of a full HW/SW H.264 encoder. The latest reference software is modified by allowing selected computationally extensive modules to be optionally executed in emulated hardware. SystemC is used for hardware modeling. The proposed strategy enables us to perform early functional verification and conformance analysis of the IP-blocks at the system level of abstraction.
This paper describes a DSP implementation of a realtime 3D sound localization algorithm. A distinctive feature of this implementation is that the audible frequency band is divided into three on the basis of the analys...
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ISBN:
(纸本)0780371453
This paper describes a DSP implementation of a realtime 3D sound localization algorithm. A distinctive feature of this implementation is that the audible frequency band is divided into three on the basis of the analysis of the effects of sound diffraction, such that in these three subbands specific schemes of the 3D sound localization are devised with the use of an IIR filter, three parametric equalizers, and a comb filter, respectively, so as to be run realtime on a 16-bit fixed-point DSP at a low frequency of 50 MHz, maintaining the high-quality sound localization. As a result, this 3D sound localization scheme can be applied to mobile applications such as headphones and a handy-phone with the use of an embedded DSP.
In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OF...
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This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for la...
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ISBN:
(纸本)9781509033614
This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for labelling problems which is hardware friendly. There are few researches focus on BP implementation in large disparity range stereo matching problems, since traditional belief propagation hardware implementations suffer from a server trade-off between hardware efficiency and short critical path while the disparity range is larger than 64. In this paper, we eliminate the redundancy of previous BP implementation and propose an efficient architecture without introducing any delay overhead which is more suitable for large disparity range cases. As a result, the hardware complexity is reduced from O(L-2) to O(Llog(2) L), where L is the disparity range. We use a time-area term to demonstrate the trade-off between various architectures, results show that the proposed one can reach 49.6% and 71.2% reduction compared to the state-of-the-art implementation[1] with disparity ranges 64 and 128 respectively.
Many curricula include separate classes in both digital signalprocessing (DSP) theory and very high-speed integtrated circuit hardware description language (VHDL) modeling;however, there are few opportunities given t...
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Many curricula include separate classes in both digital signalprocessing (DSP) theory and very high-speed integtrated circuit hardware description language (VHDL) modeling;however, there are few opportunities given to students to combine these two skills into a working knowledge of DSP hardware design. A pedagogical framework has been developed whereby students can leverage their previous knowledge of DSP theory and VHDL hardware design techniques to design, simulate, synthesize, and test digital signalprocessingsystems. The synthesized hardware is implemented on field-programmable gate arrays (FPGAs), which provide a fast and cost-effective way of prototyping hardware systems in a laboratory environment. This framework allows students to expand their previous knowledge into a more complete understanding of the entire design process from specification and simulation through synthesis and verification. Students are exposed to different aspects of signalprocessingdesign, including finite precision, parallel implementation, and implementation cost tradeoffs.
Based on the radix4 Booth algorithm, a scheme that integrates tap folding and coefficient folding is proposed to design a programmable Finite Impulse Response (FIR) architecture with low power dissipation. In addition...
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ISBN:
(纸本)9781424403820
Based on the radix4 Booth algorithm, a scheme that integrates tap folding and coefficient folding is proposed to design a programmable Finite Impulse Response (FIR) architecture with low power dissipation. In addition, without increasing hardware complexity and degrading computational performance, the effective selection on input data is realized to lower the operating frequencies of the latches and multiplexers involved with the input data. With the reduction on the frequency of the input data being selected to the Booth decoders, the power consumed in the Booth decoders can be also minimized. The proposed and conventional FIR architectures are implemented using the TSMC 0.18 mu m CMOS technology. The areas and power consumption of these architectures are analyzed and compared. Under the same specifications and throughput rate, the results revealed that in comparison to the conventional architectures, the proposed FIR architecture not only saves about 18.18% to 39.19% of area occupied, it also reduces 14.23% to 25.56% in power consumption.
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