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作者： Nguyen, Tien Daly, Aengus Gomez-Quintana, Sergi O'Sullivan, Feargal Temko, Andriy Popovici, Emanuel Univ Coll Cork Dept Elect & Elect Engn Coll Rd Cork T12 K8AF Ireland

Detecting seizures in neonates requires continuous electroencephalography (EEG) monitoring, a costly process that demands trained experts. Although recent advancements in machine learning offer promising solutions for automated seizure detection, the opaque nature of these algorithms poses significant challenges to their adoption in healthcare settings. A prior study demonstrated that integrating machine learning with sonification-an interpretation method that converts bio-signals into sound-can mitigate the black-box problem while enhancing seizure detection performance. This AI-assisted sonification algorithm can provide a valuable complementary tool in seizure monitoring besides the traditional visualization method. A low-power and affordable implementation of the algorithm is presented in this study using a microcontroller. To improve its practicality, we also introduce a real-time design that allows the sonification algorithm to function in parallel with data acquisition. The system consumes 12 mW in average, making it suitable for a battery-powered device.

关键词： Electroencephalography Sonification Pediatrics Real-time systems Instruction sets signal processing algorithms Vocoders Monitoring Interpolation Detection algorithms Artificial intelligence biomedical monitoring biomedical signal processing electroencephalography embedded software Edge AI internet of medical things machine learning microprocessors real-time systems sonification signal processing algorithms

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Enabling Model-Based design for Real-Time Spike Detection

IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY

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ieee OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页

作者： Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy

Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that poses challenges in terms of development, documentation, and long-term maintenance. Methods: We adopted an alternative strategy centered on Model-Based design (MBD) to simplify the creation of neuroengineering systems and reduce the entry barriers. MBD offers distinct advantages by streamlining the design workflow, from modelling to implementation, thus facilitating the development of intricate systems. A spike detection algorithm has been implemented on a commercially available system based on a Field-Programmable Gate Array (FPGA) that combines neural probe electronics with configurable integrated circuit. The entire process of data handling and data processing was performed within the Simulink environment, with subsequent generation of hardware description language (HDL) code tailored to the FPGA hardware. Results: The validation was conducted through in vivo experiments involving six animals and demonstrated the capability of our MBD-based real time processing (latency <= 100.37 s) to achieve the same performances of offline spike detection. Conclusions: This methodology can have a significant impact in the development of neuroengineering systems by speeding up the prototyping of various system architectures. We have made all project code files open source, thereby providing free access to fellow scientists interested in the development of neuroengineering systems.

关键词： Hardware design languages Software packages Codes Field programmable gate arrays Computer architecture Hardware signal processing algorithms Neural engineering signal processing Computational modeling in vivo experiments HDL coder Field-Programmable Gate Array (FPGA) neuroengineering

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An Efficient Brain-Switch for Asynchronous Brain-Computer Interfaces

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ieee TRANSACTIONS ON BIOMEDICAL CIRCUITS AND systems 2025年第1期19卷 130-141页

作者： Valencia, Daniel Mercier, Patrick P. Alimohammad, Amir San Diego State Univ Dept Elect & Comp Engn San Diego CA 92182 USA Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA

Intracortical brain computer interfaces (iBCIs) utilizing extracellular recordings mainly employ in vivo signal processing application-specific integrated circuits (ASICs) to detect action potentials (spikes). Conventionally, "brain-switches" based on spiking activity have been employed to realize asynchronous (self-paced) iBCIs, estimating when the user involves in the underlying BCI task. Several studies have demonstrated that local field potentials (LFPs) can effectively replace action potentials, drastically reducing the power consumption and processing requirements of in vivo ASICs. This article presents the first LFP-based brain-switch design and implementation using gated recurrent neural networks (RNNs). Compared to the previously reported brain-switches, our design requires no exhaustive learning phase for the estimation of optimal recording channels or frequency band selection, making it more applicable to practical asynchronous iBCIs. The synthesized ASIC of the designed in vivo LFP-based feature extraction unit, in a standard 180-nm CMOS process, occupies only 0.09 mm2 of silicon area, and the post place-and-route synthesis results indicate that it consumes 91.87 nW of power while operating at 2 kHz. Compared to the previously published ASICs, the proposed LFP-based brain-switch consumes the least power for in vivo digital signal processing and achieves comparable state estimation performance to that of spike-based brain-switches.

关键词： Neurons Electrodes Decoding Silicon Recording Extracellular Feature extraction Application-specific integrated circuits brain-computer interfaces local field potentials neural signal processing

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Bit-Limited Sub-Nyquist Pulse-Doppler Radar

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ieee TRANSACTIONS ON AEROSPACE AND ELECTRONIC systems 2025年第2期61卷 2340-2354页

作者： Wang, Yating Xi, Feng Chen, Shengyao Liu, Zhong Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Peoples R China

Pulse-Doppler (PD) radars, which prefer to operate with large bandwidth signals to attain superior range resolution, are widely used due to their superior performance in target detection and parameter estimation. However, the increasing data flow of such radar systems induced by large bandwidth presents significant challenges to signal processing and hardware implementation, particularly concerning analog-to-digital converters (ADCs), which are tasked with converting high-bandwidth inputs into digital representations at or above the Nyquist rate. In this work, we introduce a hybrid analog-digital processing architecture, which implements sub-Nyquist sampling as well as low-bit quantization, specifically tailored for PD radar applications. We refer to the designed architecture as the bit-limited sub-Nyquist pulse-Doppler radar (BiLiPD) receiver, designed with cost-efficiency in mind, utilizing low-rate and low-resolution ADCs to reduce both cost and power consumption. Specifically, the received radar echoes are acquired under the sub-Nyquist sampling framework, and then, quantized with low-resolution ADCs. The building modules of the proposed BiLiPD receiver, including the analog preprocessing, the ADCs, and the digital processing, are jointly designed to mitigate the challenges posed by sub-Nyquist sampling and low-bit quantization. We incorporate structural constraints into the design problem, formulating it under the task-based quantization framework and employing gradient descent methods for its solution. Our simulation results illustrate that the proposed BiLiPD receiver operating under low-rate low-bit constraints is capable of accurately recovering target parameters, with its target recovery performance approaching that of classic PD processing operating with unlimited resolution ADCs while notably outperforming that employing task-ignorant low-bit quantization.

关键词： Radar Quantization (signal) Receivers Doppler radar Radar signal processing Radar cross-sections Bandwidth signal resolution signal processing Hardware Bit-limited analog-to-digital converters (ADCs) compressive sensing (CS) sub-Nyquist sampling task-based quantization

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High-Throughput Barcode Fluorescence Sensor signal Rapid processing: Integration of Multiple Algorithms and Visualization implementation

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ieee SENSORS JOURNAL 2025年第2期25卷 3348-3357页

作者： Wang, Baole Geng, Qingfubo Zhan, Weihe Geng, Zhaoxin Minzu Univ China Sch Informat Engn Beijing 100081 Peoples R China Minzu Univ China Sch Informat Engn Key Lab Ethn Language Intelligent Anal & Secur Gov Beijing 100081 Peoples R China

The field of fluorescence barcode sensor signal processing is the focus, with the development of a high-throughput fluorescence detection visualization platform that integrates multiple efficient fluorescence array localization algorithms, including manual mask positioning, an optimized k-means++ algorithm, and a projection iterative algorithm designed based on fluorescence image projection data. Comprehensive monitoring, real-time adjustment, and integrated data analysis are enabled by the platform, significantly enhancing the accuracy, speed, and convenience of fluorescence image processing. Experimental results demonstrate that the projection iterative algorithm excels in both accuracy and processing speed, achieving a mean squared error (mse) of 6.42130, which is 20.97% lower than that of the k-means++ algorithm, and a processing time of 1095 ms, which is 80.21% and 94.37% faster than the mask positioning and k-means++ algorithms, respectively. Furthermore, evaluation of different fitting algorithms shows that sigmoid curve fitting performs best across various metrics, with an R-2 value as high as 0.987480, indicating excellent data interpretability and fitting accuracy. Overall, precise, rapid, and efficient signal processing in high-throughput fluorescence detection is achieved, providing robust technical support and innovative tools for related research fields.

关键词： Fluorescence Sensors Accuracy Software systems Gray-scale Noise Clustering algorithms signal processing algorithms Sensor arrays Image sensors Barcode biochip fluorescence image high throughput sensor signal software design

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An Efficient FPGA implementation of Approximate Nearest Neighbor Search

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ieee TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2025年

作者： Song, Yifeng Liu, Chenjie Zhang, Rongrong Zhu, Danyang Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China PrimeAI Ltd Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

Approximate nearest neighbor search (ANNS) plays an important role in modern artificial intelligence (AI) systems, being extensively utilized in search engines, advertising, and recommendation systems. With the advent of large language models (LLMs), ANNS is increasingly finding applications in edge scenarios such as personal assistants. The demand for efficient and fast ANNS solutions is, therefore, more pressing than ever. In this article, we propose a scalable and efficient field-programmable gate array (FPGA) implementation of ANNS based on the inverted file with product quantization (IVF-PQ) algorithm, thus marking the first hardware implementation supporting up to 1024-D datasets. First, we devise a novel architecture for the Top-K module, capable of processing multiple input data streams simultaneously and linearly increasing throughput. Second, we adjust the data precision in several parts of our design, thus achieving obvious performance improvement without losing much recall. Moreover, we introduce a flexible distance calculation (Distance Cal) module that can be reused for various computational tasks at different query stages. We code our design in Verilog and implement it on Xilinx Alveo U280. The experimental results show that our search latency can be as low as 0.0071 ms at a 94% recall, while the power is 19.80 W. Compared to the state-of-the-art application-specified integrated circuit (ASIC) implementations, our design delivers a 4.5x speedup in latency and a 20% reduction in energy consumption.

关键词： Vectors Indexes Field programmable gate arrays Databases Hardware Artificial intelligence Codes Quantization (signal) Clustering algorithms Approximation algorithms Approximate nearest neighbor search (ANNS) field-programmable gate array (FPGA) hardware inverted file with product quantization (IVF-PQ)

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Acceleration of Fast Sample Entropy for FPGAs

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ieee TRANSACTIONS ON COMPUTERS 2025年第1期74卷 1-14页

作者： Chen, Chao Liu, Chengyu Li, Jianqing da Silva, Bruno Southeast Univ Sch Instrument Sci & Engn Nanjing 210096 Peoples R China Vrije Univ Brussel VUB Dept Elect & Informat ETRO B-1050 Brussels Belgium Vrije Univ Brussel VUB Dept Elect & Informat ETRO B-1050 Brussels Belgium

Complexity measurement, essential in diverse fields like finance, biomedicine, climate science, and network traffic, demands real-time computation to mitigate risks and losses. Sample Entropy (SampEn) is an efficacious metric which quantifies the complexity by assessing the similarities among microscale patterns within the time-series data. Unfortunately, the conventional implementation of SampEn is computationally demanding, posing challenges for its application in real-time analysis, particularly for long time series. Field Programmable Gate Arrays (FPGAs) offer a promising solution due to their fast processing and energy efficiency, which can be customized to perform specific signal processing tasks directly in hardware. The presented work focuses on accelerating SampEn analysis on FPGAs for efficient time-series complexity analysis. A refined, fast, Lightweight SampEn architecture (LW SampEn) on FPGA, which is optimized to use sorted sequences to reduce computational complexity, is accelerated for FPGAs. Various sorting algorithms on FPGAs are assessed, and novel dynamic loop strategies and micro-architectures are proposed to tackle SampEn's undetermined search boundaries. Multi-source biomedical signals are used to profile the above design and select a proper architecture, underscoring the importance of customizing FPGA design for specific applications. Our optimized architecture achieves a 7x to 560x speedup over standard baseline architecture, enabling real-time processing of time-sensitive data.

关键词： Field programmable gate arrays Computer architecture Complexity theory Sorting Entropy Time series analysis Real-time systems Field programmable gate array (FPGA) high-level synthesis (HLS) design optimization signal processing information entropy sample entropy fast computation

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A Comprehensive design Framework for UE-side and BS-Side RIS Deployments

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ieee WIRELESS COMMUNICATIONS 2025年

作者： Raeisi, Mahmoud Khaleel, Aymen Ilter, Mehmet C. Gerami, Majid Basar, Ertugrul Koc Univ Wireless Commun Istanbul Turkiye Koc Univ Istanbul Turkiye Huawei Lund Res Ctr Lund Sweden Tampere Univ Tampere Finland Huawei Technol Sweden AB Solna Sweden Koc Univ Dept Elect & Elect Engn Istanbul Turkiye

Integrating reconfigurable intelligent surfaces (RISs) in emerging communication systems is a fast-growing research field that has recently earned much attention. While implementing RISs near the base station (BS), that is, BS-side RIS, or user equipment (UE), that is, UE-side RIS, exhibit optimum performance, understanding the differences between these two deployments in terms of the system design perspective needs to be clarified. Critical design parameters, such as RIS size, phase shift adjustment, control link, and element type (passive/active), require greater clarity across these scenarios. Overlooking the intricacies of such critical design parameters in light of 6G demands endangers practical implementation, widening the gap between theoretical insights and practical applications. In this regard, our study investigates the impact of each RIS deployment strategy on the anticipated 6G requirements and offers tailored RIS design recommendations to fulfill these forward- looking requirements. Through this, we clarify the practical distinctions and propose a comprehensive framework for differentiating between BS-side and UE-side RIS scenarios in terms of their design parameters. Highlighting the unique needs of each and the potential challenges ahead, we aim to fuse the theoretical underpinnings of RIS with tangible implementation considerations, propelling progress in both the academic sphere and the industry.

关键词： Reconfigurable intelligent surfaces Reliability Wireless communication 6G mobile communication Hardware Energy efficiency Array signal processing Channel estimation Backhaul networks Spectral efficiency

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