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A Comprehensive design Framework for UE-side and BS-Side RIS Deployments

ieee WIRELESS COMMUNICATIONS 2025年

作者： Raeisi, Mahmoud Khaleel, Aymen Ilter, Mehmet C. Gerami, Majid Basar, Ertugrul Koc Univ Wireless Commun Istanbul Turkiye Koc Univ Istanbul Turkiye Huawei Lund Res Ctr Lund Sweden Tampere Univ Tampere Finland Huawei Technol Sweden AB Solna Sweden Koc Univ Dept Elect & Elect Engn Istanbul Turkiye

Integrating reconfigurable intelligent surfaces (RISs) in emerging communication systems is a fast-growing research field that has recently earned much attention. While implementing RISs near the base station (BS), that is, BS-side RIS, or user equipment (UE), that is, UE-side RIS, exhibit optimum performance, understanding the differences between these two deployments in terms of the system design perspective needs to be clarified. Critical design parameters, such as RIS size, phase shift adjustment, control link, and element type (passive/active), require greater clarity across these scenarios. Overlooking the intricacies of such critical design parameters in light of 6G demands endangers practical implementation, widening the gap between theoretical insights and practical applications. In this regard, our study investigates the impact of each RIS deployment strategy on the anticipated 6G requirements and offers tailored RIS design recommendations to fulfill these forward- looking requirements. Through this, we clarify the practical distinctions and propose a comprehensive framework for differentiating between BS-side and UE-side RIS scenarios in terms of their design parameters. Highlighting the unique needs of each and the potential challenges ahead, we aim to fuse the theoretical underpinnings of RIS with tangible implementation considerations, propelling progress in both the academic sphere and the industry.

关键词： Reconfigurable intelligent surfaces Reliability Wireless communication 6G mobile communication Hardware Energy efficiency Array signal processing Channel estimation Backhaul networks Spectral efficiency

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Hybrid Beamforming for Millimeter-Wave Massive Grant-Free Transmission

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ieee TRANSACTIONS ON COMMUNICATIONS 2025年第3期73卷 2061-2076页

作者： Sun, Gangle Yi, Xinping Wang, Wenjin Xu, Wei Jin, Shi Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Peoples R China Purple Mt Labs Nanjing 211100 Peoples R China

The increasing demands for spectral resources in emerging massive machine-type communication applications necessitate the implementation of massive grant-free transmission in the millimeter-wave (mmWave) band. This paper proposes two efficient receive analog beamforming design algorithms for mmWave massive grant-free transmission under hybrid beamforming architectures, intending to optimize spectral efficiency and access probability, respectively. Specifically, we first express the spectral efficiency of mmWave massive grant-free transmission systems and then derive an analytically tractable approximation using the random matrix theory. Following this, an alternating optimization method is employed to design the receive beamforming matrix efficiently. Additionally, we provide the formulation of access probability for mmWave massive grant-free transmission, whose explicit expression is approximately derived through the Gaussian approximation. Building upon this, we utilize a convex hull relaxation-based optimization method to optimize the beamforming matrix. The effectiveness of our proposed beamforming design algorithms in improving spectral efficiency and access probability is validated through extensive simulation experiments.

关键词： Array signal processing Millimeter wave communication Vectors Radio frequency Uplink Spectral efficiency Computer architecture Access probability analog beamforming design grant-free massive machine-type communication millimeter-wave systems spectral efficiency

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design and Empirical Validation of a Low-Cost Outdoor mmWave Altimetry Test Bench for UAS

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ieee ACCESS 2025年 13卷 56034-56044页

作者： Derawi, Mohammad Awan, Maaz Ali Sahin, Adem Dalveren, Yaser Ozdur, Ibrahim Kara, Ali Norwegian Univ Sci & Technol Dept Elect Syst N-2815 Gjovik Norway Gazi Univ Dept Elect & Elect Engn TR-06570 Ankara Turkiye TOBB ETU Dept Elect & Elect Engn TR-06570 Ankara Turkiye Izmir Bakircay Univ Dept Elect & Elect Engn TR-35665 Izmir Turkiye

The increasing adoption of unmanned aerial systems (UAS) in diverse urban applications necessitates reliable and precise altimetry solutions for situational awareness and landing safety. Despite significant advancements in the realm of waveform design and signal processing, empirical validation of millimeter wave (mmWave) Frequency Modulated Continuous Wave (FMCW) waveforms for altimetry use case remains a critical gap in literature. This study argues the necessity of empirical validation of candidate FMCW waveforms by proposing an inexpensive and practical outdoor test bench. The multipath propagation model for the said test bench is presented along with a simplified testing methodology suitable for implementation on contemporary mmWave automotive radars. The specifics of the test bench are deliberated where a flat concrete wall with a sufficiently large surface area is employed as a static target. The underpinnings established by this body of work shall serve dynamic testing on a drone platform against various terrain types in the next phase of research. The experimental results demonstrate the potential of practical use of mmWave altimetry on UAS in urban deployment.

关键词： Millimeter wave communication Testing Radar Reflection Altimetry Costs Measurement Clutter signal to noise ratio Laboratories Outdoor test bench mmWave altimetry FMCW UAS

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A Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers

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ieee TRANSACTIONS ON BIOMEDICAL CIRCUITS AND systems 2025年第1期19卷 142-152页

作者： Busia, Paola Scrugli, Matteo Antonio Jung, Victor Jean-Baptiste Benini, Luca Meloni, Paolo Univ Cagliari DIEE I-09123 Cagliari Italy Swiss Fed Inst Technol Integrated Syst Lab CH-8000 Zurich Switzerland Univ Bologna DEI I-40126 Bologna Italy

Wearable systems for the continuous and real-time monitoring of cardiovascular diseases are becoming widespread and valuable assets in diagnosis and therapy. A promising approach for real-time analysis of the electrocardiographic (ECG) signal and the detection of heart conditions, such as arrhythmia, is represented by the transformer machine learning model. Transformers are powerful models for the classification of time series, although efficient implementation in the wearable domain raises significant design challenges, to combine adequate accuracy and a suitable complexity. In this work, we present a tiny transformer model for the analysis of the ECG signal, requiring only 6k parameters and reaching 98.97% accuracy in the recognition of the 5 most common arrhythmia classes from the MIT-BIH Arrhythmia database, assessed considering 8-bit integer inference as required for efficient execution on low-power microcontroller-based devices. We explored an augmentation-based training approach for improving the robustness against electrode motion artifacts noise, resulting in a worst-case post-deployment performance assessment of 98.36% accuracy. Suitability for wearable monitoring solutions is finally demonstrated through efficient deployment on the parallel ultra-low-power GAP9 processor, where inference execution requires 4.28ms and 0.09mJ.

关键词： Transformers Arrhythmia Electrocardiography Noise Monitoring Heart beat Real-time systems transformer wearable monitoring

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Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations

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ieee TRANSACTIONS ON CIRCUITS AND systems I-REGULAR PAPERS 2025年

作者： Verma, Anu Das, Bishnu Prasad Indian Inst Technol IIT Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttarakhand India

Trigonometric functions are widely used in various scientific and engineering applications, including digital signal processing. This article proposes a low-complexity low-latency reconfigurable CORDIC (COordinate Rotation Digital Computer) algorithm that computes trigonometric functions, which is based on a novel angle set of microrotations. The CORDIC algorithm is an iterative algorithm that reduces the performance due to the high latency of computation. The proposed pipelined scale-free CORDIC algorithm computes the functions in only four iterations with an optimized angle set of microrotations with high accuracy. It can be configured in two modes with different trajectories 1) rotation-mode;and 2) vectoring-mode for circular and hyperbolic trajectories. On-board FPGA implementation of the proposed architecture consumes 34.95% less register, 48.12% less occupied slices, 19.06% less LUTs, 66.51% less slice-latency product (SLP), 59.29% less LUT-latency product (LLP), and 71.23% less register-latency product (RLP) compared to the best existing state-of-the-art CORDIC architectures. Moreover, the latency of the proposed architecture is 72.34% less than the best of existing designs. Besides, the parasitic-extracted layout simulation results of the proposed design across different word lengths are reported in TSMC 65-nm CMOS technology for the validation of the proposed architecture.

关键词： Computer architecture Accuracy Hardware Trajectory Convergence Taylor series Pipelines Complexity theory Table lookup signal processing algorithms Coordinate rotation digital computer (CORDIC) reconfigurable CORDIC FPGA ASIC

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An End-to-End Bundled-Data Asynchronous Circuits design Flow: From RTL to GDS

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ieee TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2025年第1期33卷 154-167页

作者： Wang, Jinghai Xiao, Shanlin Luo, Jilong Li, Bo Zhou, Lingfeng Yu, Zhiyi Sun Yat Sen Univ Sch Microelect Sci & Technol Zhuhai 519082 Peoples R China Sun Yat Sen Univ Sch Microelect Sci & Technol Guangdong Prov Key Lab Optoelect Informat Proc Chi Zhuhai 519082 Peoples R China

Asynchronous circuits with low power and robustness are revived in emerging applications such as the Internet of Things (IoT) and neuromorphic chips, thanks to clock-less and event-driven mechanisms. However, the lack of mature computer-aided design (CAD) tools for designing large-scale asynchronous circuits results in low design efficiency and high cost. This article proposes an end-to-end bundled-data (BD) asynchronous circuit design flow, which can facilitate building asynchronous circuits, even if the designer has little or no asynchronous circuit foundation. Three features that enable this are: 1) a lightweight circuit converter developed in Python can convert circuits from synchronous descriptions to corresponding asynchronous ones at register transfer level (RTL). Desynchronization flow helps designers maintain a "synchronization mentality" to construct asynchronous circuits;2) a synchronization-like verification method is proposed for asynchronous circuits so that it can be functionally verified before synthesis. Avoids the risk of rework after logic defects are discovered during the synthesis and implementation, as asynchronous circuits often cannot be simulated until gate-level (GL) netlist generation;and 3) the whole implementation flow from RTL to graphic data system (GDS) is based on commercial electronic design automation (EDA) tools. Similar to the design flow of synchronous circuits, it helps designers implement asynchronous circuits with "synchronization habits." Furthermore, to validate this methodology, two asynchronous processors were, respectively, implemented and evaluated in the TSMC 28-nm CMOS process. Compared to their synchronous counterparts, the general-purpose asynchronous RISC-V processor achieves 20.5% power savings. And the domain-specific asynchronous spiking neural network (SNN) accelerator achieves 58.46% power savings and 2.41x energy efficiency improvement at 70% input spike sparsity.

关键词： Asynchronous circuits Circuits Timing Program processors Clocks Protocols Optical signal processing Encoding Logic gates Internet of Things design flow low power RISC-V spiking neural networks (SNNs)

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Decentralized Likelihood Ascent Search-Aided Detection For Distributed Large-Scale MIMO systems

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ieee Transactions on Wireless Communications 2025年第5期24卷 4160-4173页

作者： Chen, Qiqiang Wang, Zheng Qi, Chenhao Gao, Zhen Huang, Yongming Niyato, Dusit Southeast University School of Information Science and Engineering Nanjing210096 China Advanced Technology Research Institute Jinan250307 China Zhuhai519088 China Yangtze Delta Region Academy Jiaxing314019 China Nanyang Technological University Singapore

In this paper, we propose the decentralized likelihood ascent search (DLAS)-aided detection for the distributed large-scale multiple-input multiple-output (MIMO) systems to achieve more remarkable performance gains. With the help of DLAS, traditional distributed iterative methods are able to achieve better performance than the linear detection schemes such as ZF and MMSE. According to analysis, we derive the equivalent noise and the post-processing SNR for DLAS. More importantly, based on them, we demonstrate that the proposed DLAS-aided detection achieves the full received diversity. To further facilitate its implementation in practice, we design the decentralized effective ring (DER) architecture with significantly reduced bandwidth requirement and better parallel computation. Finally, simulation results demonstrate that the proposed DLAS-aided detection attains the same received diversity as ML detection while surpassing state-of-the-art decentralized schemes in terms of BER performance, with reduced complexity and bandwidth costs. © 2002-2012 ieee.

关键词： MIMO Bandwidth Vectors Computer architecture Antennas signal detection Costs Complexity theory Antenna arrays Uplink

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A Universal Methodology of Complex Number Computation for Low-Complexity and High-Speed implementation

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ieee TRANSACTIONS ON CIRCUITS AND systems I-REGULAR PAPERS 2025年第3期72卷 1308-1320页

作者： Wang, Yu Zhang, Jin Wu, Youlong Lyu, Fei Luo, Yuanyong Nanjing Xiaozhuang Univ Sch Elect Engn Nanjing 211171 Peoples R China Jinling Inst Technol Sch Elect & Informat Engn Nanjing 211169 Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Integrated Circuits Nanjing 211106 Peoples R China Nanjing Univ Sch Phys Nanjing 210093 Peoples R China Huawei Corp Dept Turing Architecture Design Linx Lab HiSilicon Shenzhen 518129 Peoples R China

In complex-valued neural network (CVNN) applications, complex number calculations require high performance rather than high precision. However, most previous studies focused on high-precision approaches, which have low speed and high hardware costs. This paper proposes a universal methodology of complex number computation for low-complexity and high-speed implementation. The proposed methodology is based on the piecewise linear (PWL) method and can be used for different types of complex number computations. Considering that multiplication operations consume considerable resources, multiplication, fused square-add (FSA) and fused multiply-add (FMA) operations are the focus of optimization. The partial products of the square operation are reduced by folding and merging techniques because of their symmetry in the FSA operation. The partial products of the multiplication and FMA operations are reduced via Booth encoding. In addition, the partial products are further reduced by the proposed step-by-step truncation method. The proposed segmenter, which simulates the hardware implementation, automatically divides the nonlinear functions in the complex number computations into the smallest number of segments according to the required precision. The results show that the proposed approach improves performance and reduces hardware costs compared with the state-of-the-art methods for complex number calculations involving square roots, reciprocals and logarithms.

关键词： Hardware Image segmentation Software Neural networks Costs signal processing algorithms Power demand Optimization Merging Encoding Piecewise linear (PWL) approximation method computation for complex numbers step-by-step truncation square root calculation of complex numbers reciprocal calculation of complex numbers logarithm calculation of complex numbers

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Feature-PLPD: Feature-Point and Line Points Detection for Real-Time Embedded Visual Odometry-based systems

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ieee signal processing Letters 2025年 32卷 1890-1894页

作者： Mamri, Ayoub Hadri, Abdelhafid El Benallegue, Abdelaziz Universitè Paris-Saclay UVSQ LISV Vèlizy-Villacoublay 78124 France

Detection of interest features is a fundamental pre-processing task for visual odometry and visual simultaneous localization and mapping. The combination of line segments and corners is a trend for those applications, and it is challenging to meet real-time constraints. To pursue this goal, this letter presents a novel points and line points feature detection (PLPD) algorithm designed to be highly efficient and accurate for real-time VO-based systems. The proposed algorithm adopts a novel Multi-level Edge Detector (MED) based on gradient intensity and structure tensor that is not confined solely to extracting corners, but rather, it exploits feature-line points properties to extract long-line segments directly without merging collinear fragment segments. The main focus of this work is to fulfill the real-time and embeddability constraints of our proposed method by adopting the GPU-aware software design for a suitable implementation in GPU-based embedded heterogeneous architecture. Based on this, we exhibit extensive benchmarking with other state-of-the-art algorithms for feature-line segment extraction and corner detection, showing the efficiency of the proposed algorithm and ensuring a real-time performance up to 33 FPS using our dataset. © 1994-2012 ieee.

关键词： Program processors

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Globally Optimal Resource Allocation design for Discrete Phase Shift IRS-Assisted Multiuser Networks With Perfect and Imperfect CSI

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ieee TRANSACTIONS ON WIRELESS COMMUNICATIONS 2025年第2期24卷 1306-1324页

作者： Wu, Yifei Xu, Dongfang Ng, Derrick Wing Kwan Schober, Robert Gerstacker, Wolfgang Friedrich Alexander Univ Erlangen Nurnberg FAU Inst Digital Commun D-91054 Erlangen Germany Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Univ New South Wales Sch Elect Engn & Telecommun Sydney NSW 2052 Australia

Intelligent reflecting surfaces (IRSs) are a promising low-cost solution for achieving high spectral and energy efficiency in future communication systems by enabling the customization of wireless propagation environments. Despite the plethora of research on resource allocation design for IRS-assisted multiuser wireless communication systems, the optimal design and the corresponding performance upper bound are still not fully understood. To bridge this gap in knowledge, in this paper, we investigate the optimal resource allocation design for IRS-assisted multiuser multiple-input single-output (MISO) systems employing practical discrete IRS phase shifters. In particular, we jointly optimize the beamforming vector at the base station (BS) and the discrete IRS phase shifts to minimize the total transmit power for the cases of perfect and imperfect channel state information (CSI) knowledge. To this end, two novel algorithms based on the generalized Benders decomposition (GBD) method are developed to obtain the globally optimal solution for perfect and imperfect CSI, respectively. Moreover, to facilitate practical implementation, we propose two corresponding low-complexity suboptimal algorithms with guaranteed convergence by capitalizing on successive convex approximation (SCA). In particular, for imperfect CSI, we adopt a bounded error model to characterize the CSI uncertainty and propose a new transformation to convexify the robust quality-of-service (QoS) constraints. Our numerical results confirm the optimality of the proposed GBD-based algorithms for the considered system for both perfect and imperfect CSI. Furthermore, we unveil that both proposed SCA-based algorithms can attain a locally optimal solution within a few iterations. Moreover, compared with the state-of-the-art solution based on alternating optimization (AO), the proposed low-complexity SCA-based schemes achieve a significant performance gain, especially for moderate-to-large numbers of IRS elements.

关键词： Wireless communication Resource management Optimization Phase shifters Array signal processing Vectors Channel estimation Approximation algorithms Quality of service Convergence Generalized Benders decomposition method optimal resource allocation intelligent reflecting surface

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