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ieee workshop on signal processing systems (SIPS)

作者： J.-P. Delahaye J. Palicot P. Leray Campus de Rennes Av. de la Boulais BP 81127 IETR/Supelec Cesson-Sevigne France

This paper presents a functional model based on a hierarchical architecture template meeting with software defined radio system requirements (SDR systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD uplink, GSM uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of a heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.

关键词： Software radio Computer architecture Application software Hardware Resource management Field programmable gate arrays Reconfigurable architectures Baseband Proposals Software standards

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Predictive transform: A simple and optimum unified approach to signal modeling, coding, estimation, and control

Predictive transform: A simple and optimum unified approach ...

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Proceedings of the ieee 1989 National Aerospace and Electronics Conference - NAECON 1989

作者： Feria, E.H. Coll of Staten Island City Univ of New York Staten Island NY USA

The decoder of a minimum mean-square-error predictive transform (PT) coder is found to be the key to a simple and optimum unification and transformation enhancement of well-established techniques in linear and nonlinear signal modeling, coding, estimation, and control. The fundamental property of the PT decoder that makes this possible is that the PT decoder is a whitening model of the signal that one wishes to model, encode, estimate, and/or control. In addition, the PT decoder is capable of exactly identifying a large class of linear and nonlinear whitening signal sources. Hence, this whitening signal modeling property of the PT decoder allows its integration with well-known signal-processing techniques such as Kalman estimation and linear quadratic Gaussian (LQG) control. An added bonus of this integration is the appearance of a transformation mechanism that leads to significant simplifications of the Kalman estimator as well as the LQG controller. The transformation-enhanced Kalman estimator is illustrated with monochrome images embedded in additive white noise and is found to produce a design and implementation complexity that is simpler than that of a classical Kalman estimator - without transformation - by a factor that approaches four in the smoothing case.

关键词： signal processing

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A Parallel Radix-4 Fast Fourier Transform Computer

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ieee Transactions on Computers 1975年第1期C-24卷 80-92页

作者： Corinthios, Michael J. Smith, Kenneth C. Yen, Jui L. Department of Electrical Engineering Ecole Polytechnique Université dé Montréal Montreal P.Q. Canada Department of Electrical Engineering University of Toronto Toronto Ont. Canada

The organization and functional design of a parallel radix-4 fast Fourier transform (FFT) computer for real-time signal processing of wide-band signals is introduced. Several machine oriented FFT algorithms obtained by factoring the discrete Fourier transform (DFT) to an arbitrary radix and which are well suited for the organization of parallel wired-in processers are considered. This class of machine oriented algorithms is distinguished by the fact that it yields machine implementations ranging from fully hard-wired serial sequential processors to partially wired-in cascade processors with no feedback and with a level of parallelism that is proportional to the radix of implementation. Moreover, this class of algorithms can yield the computed Fourier coefficients in a properly ascending order without the need for pre- or postordering of data. The organization of a system for digital-spectral and time-series analysis implementing a high-speed algorithm is then outlined. It is shown that doubling the processing speed by simultaneous processing of two real-valued time series in such parallel wired-in computers is possible. System considerations for reducing roundoff errors and for performing other processes based on the Fourier transform are discussed. The organization and design of a radix-4 256-word synchronous sequential FFT signal processor which has been constructed and which performs real-time processing of signals sampled at a rate of up to 1.6 million samples/s is described. Outlined are the basic concepts which have been developed and used to minimize logic circuitry in the different units of the machine. Oscilloscope displays showing the whole sequence of computations involved in real-time Fourier transformation at a sampling frequency of 1.6 MHz are included. The FFT of 256 complex samples is computed in 160 µs. Finally, configurations of systems for signal processing using other linear transforms of generalized spectral analysis are described. © 1975, ieee.

关键词： Computer architecture convolution correlation digital filtering digital processing of signals fast Fourier transform (FFT) special-purpose computer spectral analysis time-series analysis

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design and implementation of Indonesia united portal using crowdsourcing approach for supporting conservation and monitoring of endangered species 4

Design and implementation of Indonesia united portal using c...

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4th International Conference on Interactive Digital Media, ICIDM 2015

作者： Supriadi, Irwin Prihatmanto, Ary Setijadi School of Electrical Engineering and Informatics Bandung Institute of Technology Ganesa Street 10 Bandung40132 Indonesia Electrical Engineering Department Faculty of Engineering Indonesia

ISBN: (纸本)9781509016693

This article discusses the design and implementation of web portals Indonesia United as the exchange of information on the conservation of flora and fauna Indonesia by implementing the concept of crowdsourcing. The entire community of users can access the web portal Indonesia United can be complementary, adding, correcting, and oversees the information on the web portal. Thus, Indonesia United's web portal can be used as media scrutiny for the ongoing process of preservation and violations in the field of flora and fauna, especially in the process of policy formation. Besides Indonesia United's web portal to apply gamification is a concept that adopts elements of the games into an activity or process that is not a game to improve retention, attention and interaction between users and systems. © 2015 ieee.

关键词： Portals

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Interference Suppression in a GPS Receiver with 4 Element Array design and implementation of Beamforming Algorithms

Interference Suppression in a GPS Receiver with 4 Element Ar...

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ieee/ION Position, Location and Navigation Symposium (PLANS)

作者： Dabak, Omer Can Erdem, Fatih Sonmez, Tolga Alatan, Lale Koc, S. Sencer HAVELSAN AS Ankara Turkey Middle East Tech Univ Elect & Elect Engn Dept Ankara Turkey

ISBN: (纸本)9781509020423

Global Positioning System (GPS) jammers add excessive noise to the received low power GPS signals and have capability to either weaken or completely destroy the positioning performance of GPS receivers for both civilian and military users. Researchers are actively working to develop GPS receiver systems resistant to interference sources. Our aim is to develop a system based on spatial filtering of jamming signals through the use of an active antenna array which is capable to control its radiation pattern by utilizing signal processing techniques. Array radiation pattern is controlled to maximize gain in satellite directions and to create null regions toward jammers. Adaptive beamforming methods provide necessary weighting coefficients to form desired radiation patterns using received data. In this paper, design, production and tests of an active antenna array is presented with implementation of adaptive beamforming algorithms using commercially available development boards.

关键词： GPS patch antenna CRPA antijamming beamforming nullsteering

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Energy issues in multimedia systems

Energy issues in multimedia systems

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ieee workshop on signal processing systems (SIPS)

作者： M.J. Irwin V. Narayanan Department of Computer Science and Engineering Pennsylvania State University USA

This paper presents possible optimization to reduce the energy budget for systems-on-chip (SoC) designs that will be used in next generation multimedia systems. Since future multimedia systems will include the processor core(s), the entire memory system, system buses, I/O controllers, system clocking and control and, in wireless applications, RF components, all on one chip, lowering power dissipation in next generation multimedia chips presents a number of design challenges. Possible strategies for managing the power budget in future multimedia SoCs are presented. Reducing the power consumption of the memory system, system control, and system buses are a particular focus.

关键词： Multimedia systems Control systems System buses design optimization Clocks Radio frequency Power dissipation Energy management Financial management Power system management

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2013 6th workshop on Software Engineering and Architectures for Realtime Interactive systems, SEARIS 2013;Co-located with the 2013 Virtual Reality Conference - Proceedings

2013 6th Workshop on Software Engineering and Architectures ...

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2013 6th workshop on Software Engineering and Architectures for Realtime Interactive systems, SEARIS 2013 - Co-located with the 2013 Virtual Reality Conference

ISBN: (纸本)9781479931361

The proceedings contain 6 papers. The topics discussed include: a distributed camera library design for telepresence;an actor-based distribution model for real time interactive systems;***: architecture of a polyfill implementation of XML3D;OpenFlipper - a highly modular framework for processing and visualization of complex geometric models;DRiVE: an example of distributed rendering in virtual environments;and ARML 2.0 in the context of existing AR data formats.

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A high-speed MAP architecture with optimized memory size and power consumption

A high-speed MAP architecture with optimized memory size and...

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ieee workshop on signal processing systems (SIPS)

作者： A. Worm H. Lamm N. Wehn Motorola Partnerships in Research Grant USA Institute of Microelectronic Systems University of Kaiserslautern Kaiserslautern Germany

This paper presents a novel high-speed maximum a posteriori (MAP) decoder architecture with optimized memory size and power consumption. Area and power consumption are both reduced significantly, compared to the state-of-the-art. The architecture is also capable of decoding recursive systematic convolutional codes which are the constituent codes of the revolutionary turbo-codes and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s-45 Gbit/s and above).

关键词： Memory architecture Energy consumption signal processing algorithms Maximum likelihood decoding Convolutional codes Viterbi algorithm Throughput Bit error rate Costs Convolution

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A smart camera for real-time human activity recognition

A smart camera for real-time human activity recognition

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ieee workshop on signal processing systems (SIPS)

作者： W. Wolf I. Burak Ozer Department of Electrical Engineering Princeton University Princeton NJ USA

This paper describes a smart camera system under development at Princeton University. This smart camera is designed for use in a smart room in which the camera detects the presence of a person in its visual field and determines when various gestures are made by the person. As a first step toward a VLSI implementation, we use Trimedia processors hosted by a PC. This paper describes the relationship between the algorithms used for human activity detection and the architectures required to perform these tasks in real time.

关键词： Smart cameras Humans Sensor arrays Architecture Real time systems Face recognition Motion analysis Image segmentation System testing Very large scale integration

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Topological synthesis of clock trees for VLSI-based DSP systems

Topological synthesis of clock trees for VLSI-based DSP syst...

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ieee workshop on signal processing systems (SIPS)

作者： I.S. Kourtev E.G. Friedman Department of Electrical Engineering University of Rochester Rochester NY USA University of Rochester Rochester NY US

This paper considers the problem of designing the topology of a clock distribution network for a synchronous digital signal processor so as to satisfy a non-zero clock skew schedule. A methodology and related algorithms for synthesizing the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming (ILP) problem. The proposed approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to a 64% performance improvement is attained on these circuits by exploiting non-zero clock skew throughout the synchronous system. Clock tree topologies that implement the non-zero clock skew schedule based on the synthesis algorithms presented in this paper are described for each of the benchmark circuits.

关键词： Clocks Digital signal processing Network topology Circuit topology Network synthesis signal synthesis Processor scheduling signal processing algorithms Scheduling algorithm Circuit synthesis

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