This paper outlines a space-time duality study started in 2003 and leading to a latency-information theory (LIT) that unifies information theory with a novel latency theory revealed as time-dual. While information the...
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ISBN:
(纸本)9781424436767
This paper outlines a space-time duality study started in 2003 and leading to a latency-information theory (LIT) that unifies information theory with a novel latency theory revealed as time-dual. While information theory guides the design of communication systems, latency theory does the same for recognition systems. A unified recognition-communication system is an intelligence system and LIT illuminates its design. LIT naturally arose from the author's desire to systematically address the design of a real-world intelligence system for DARPA's knowledge-aided sensor signalprocessing expert reasoning (KASSPER) program. This work has led to practical intelligence system solutions that yield outstanding target detections under severely taxing environments, while also exhibiting several orders of magnitude savings in prior-knowledge storage-space, processing-time, and implementation complexity over standard schemes. Moreover, it has led to the discovery of a mathematical-physical duality guiding life system designs.
Computation of function values is critical for designing datapath units in digital signal processors (DSP) and graphics processing units (GPU). Most function computation methods requires lookup tables (LUT) and simple...
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ISBN:
(纸本)9781538648810
Computation of function values is critical for designing datapath units in digital signal processors (DSP) and graphics processing units (GPU). Most function computation methods requires lookup tables (LUT) and simple arithmetic components. In table-bound methods, LUT size takes a significant portion of total hardware area, in particular for high-precision applications. This paper presents a new multi-level lossless table decomposition to further reduce total table size in a recently proposed hierarchical multipartite (HMP) table method which is a generation of the prior bipartite/multipartite table-addition methods. Furthermore, hardware design parameters are optimized by jointly considering all the error sources. Experimental results shows that the proposed design has the chance of further reducing the total table size of HMP, which already has significant table-size saving over previous similar designs.
Chip multi-processors (CMPs), commonly referred to as multi-core processors, are being widely adopted for deployment as part of the grid infrastructure. This change in computer architecture requires corresponding desi...
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ISBN:
(纸本)9781424416936
Chip multi-processors (CMPs), commonly referred to as multi-core processors, are being widely adopted for deployment as part of the grid infrastructure. This change in computer architecture requires corresponding design modifications in programming paradigms, including grid middleware tools, to harness the opportunities presented by multi-core processors. Simple and naive implementations of grid middleware on multi-core systems can severely impact performance. This is because programming for CMPs requires special consideration for issues such as limitations of shared bus bandwidth, cache size and coherency, and communication between threads. The goal of developing an optimized multi-threaded grid middleware for emerging multi-core processors will be realized only if researchers and developers have access to an in-depth analysis of the impact of several low level microarchitectural parameters on performance. None of the current grid simulators and emulators provide feedback at the microarchitectural level, which is essential for such an analysis. In earlier work we presented our initial results on the design and implementation of such an emulation framework, Multi-core Grid (McGrid). In this paper we extend that work and present a performance study on the effect of cache coherency, scheduling of processing threads to take advantage of data available in the cache of each core, and read and write access patterns for shared data structures. We present the performance results, analysis, and recommendations based on experiments conducted using the McGrid framework for processing XML-based grid data and documents.(1).
We introduce the TinyNode platform for wireless sensor networks. Supporting both research and industrial deployments, the platform offers communication ranges that exceed current platforms by a factor of 3 to 5, while...
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ISBN:
(纸本)1595933344
We introduce the TinyNode platform for wireless sensor networks. Supporting both research and industrial deployments, the platform offers communication ranges that exceed current platforms by a factor of 3 to 5, while consuming similar energy. It comes with a rich, practical set of hardware extensions and full TinyOS support. We describe the design choices of the TinyNode, the accompanying hardware modules, and the MAC layer implementation.
In Vehicular Ad-hoc Networks (VANETs) communication among vehicles enables new advanced driver assistance systems. Cooperative Awareness Messages (CAMs) are so frequently exchanged that deployable electronic control u...
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ISBN:
(纸本)9781467390231
In Vehicular Ad-hoc Networks (VANETs) communication among vehicles enables new advanced driver assistance systems. Cooperative Awareness Messages (CAMs) are so frequently exchanged that deployable electronic control units will not be powerful enough to process them all. Thus, most relevant CAMs need to be selected for processing. In this paper, we give an overview of relevance estimation function (REFs) for CAMs that assign them a relevance value based on metadata. We describe and evaluate an efficient message buffer and selection mechanism for most relevant CAMs. It efficiently decreases the relevance of buffered CAMs over time. We evaluate the results of the mechanism with regards to selection probability and message waiting time under realistic conditions. Furthermore, we study the runtime of various REFs using a prototypical implementation on a hardware evaluation platform. The results show that the proposed algorithms are feasible on close-to-production hardware as they quickly process most relevant CAMs.
This paper presents a lifting-domain design of filter banks with a given McMillan degree. It is based on the M-channel lifting factorizations of the degree-0 and 1 building blocks I - 2uv† and I - uv† + z-1uv†, with v...
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This paper presents a lifting-domain design of filter banks with a given McMillan degree. It is based on the M-channel lifting factorizations of the degree-0 and 1 building blocks I - 2uv† and I - uv† + z-1uv†, with v†u = 1. Paraunitariness further requires u = v. The proposed lifting factorization has a unity diagonal scaling throughout, and guarantees perfect reconstruction (PR) even when the parameters are quantized. It is shown to be minimal in terms of the minimum number of delays required. Based on the lifting factorization, regularity of the FB can be structurally imposed, and reversible, possibly multiplierless, implementation of the FB can readily be derived. design examples are given to illustrate the versatility of the proposed approach.
In this paper, we present a novel symbol detector architecture using time-domain running cross-correlation intended for impulse radio UWB communication. A bold new perspective on system designprocessing (CTBV) comple...
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Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the through...
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Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.
MEMS elements have been penetrating in each segment of life, ranging from gaming, smartphones to home automation. design and implementation of complex MEMS has become tedious. The paper describes macro modeling of 3-a...
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In Electroencephalography (EEG) classifiers, processing of EEG signals consists of extracting features from EEG signal and then processing those features to classify the signals. As of today, in most EEG processing sy...
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