This parameterized digital electronic arithmetic (PDEA) model replaces linear operations with non-linear ones. In this paper we introduce a hardware implementation of the parametric image-processing framework that wil...
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This parameterized digital electronic arithmetic (PDEA) model replaces linear operations with non-linear ones. In this paper we introduce a hardware implementation of the parametric image-processing framework that will accurately process images and speed up computation for addition, subtraction, and multiplication. Particularly, the paper presents the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations that we have developed. We also explore new microprocessor architectures to take advantage of arithmetic. The experiments executed have shown that the algorithm provides faster and better enhancements from those described in the literature. Its potential applications include computer graphics, digital signalprocessing and other multimedia applications.
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant r...
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ISBN:
(纸本)9781424445523
We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and errors due to the use of truncated redundant representation. The requirements for prescaling tables are simplified and a detailed specification of the table design is given. All principal components used in the design are described and the proposed optimizations are explained. The target platform for implementation was an Altera Stratix II FPGA [15] for which we report timing and area requirements. For a precision of 36 bits, the implementation uses 1185 ALUTs, achieving a latency of 157ns. The maximum clock frequency is 173.49MHz.
WIRELESS sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical. An example of a multi-sensor pole is shown in Fig. 1. Crucial attribute in ...
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ISBN:
(纸本)9781424446186
WIRELESS sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical. An example of a multi-sensor pole is shown in Fig. 1. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. First, the system uses its resident, or specially inserted, sensors for monitoring the environmental conditions which play a role with respect to reliability, which are sometimes referred to as health monitors. Among the physical quantities of importance are temperature, humidity and pressure. The health monitor data is periodically sampled and evaluated in the embedded digital signalprocessing (DSP) processors.
In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-based image and signalprocessingsystems on chip (SoCs). The architecture allows efficient access to structured data such as i...
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ISBN:
(纸本)9781424444182
In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-based image and signalprocessingsystems on chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define the cachepsilas practical implementation based on the application and system parameters. Complexity and performance for selected image processing algorithms like jumping snake and 2D back-projection are measured and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.
We consider the problem of distributed detection in wireless sensor networks, where sensors send their local binary decisions over error-prone wireless channels, subject to noise and fading, to a fusion center (FC) th...
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We consider the problem of distributed detection in wireless sensor networks, where sensors send their local binary decisions over error-prone wireless channels, subject to noise and fading, to a fusion center (FC) that is tasked with making the final decision. This is different from classical literature on distributed detection which provides decision and data fusion strategies assuming that sensors' local decisions are sent over orthogonal error-free channels, without taking into account fading and noise. To mitigate the deteriorating effect of fading, we propose to employ space-time coding (STC) at sensors for transmission of local decisions to the FC. We consider a communication architecture, in which the sensors are grouped into pairs, and the sensors in each pair communicate with the FC, after exchanging their binary decisions. This architecture allows us to utilize Alamouti's space-time coding (STC) at the sensors. The advantage of this scheme is to combat the fading effect via harvesting diversity and thus to improve significantly the detection reliability in the presence of fading. We derive the optimal Likelihood ratio test (LRT) fusion rule and study the effect of communication errors when sensors are exchanging decisions over inter-sensor channels on the overall detection performance. Numerical results confirm the effectiveness of the proposed scheme, and make STC a suitable candidate for signaling in distributed detection systems operating in a fading environment.
Adaptive arrays are used in smart antenna systems in order to locate and track the signals from different users. They are used to overcome multipath propagation phenomena such as reflection, diffraction and scattering...
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Adaptive arrays are used in smart antenna systems in order to locate and track the signals from different users. They are used to overcome multipath propagation phenomena such as reflection, diffraction and scattering. One of the major effects of the multipath propagation is the correlation between the received signals. This paper presents the Direction-of-Arrival (DOA) estimation algorithm with emphasis on MUltiple signal Classification (MUSIC) algorithm and MUSIC with spatial smoothing techniques to de-correlate the input signals. In addition, it presents the design and implementation of some algorithms for de-correlating the input signal using circular adaptive antenna arrays. These algorithms were implemented in MATLAB where the different parameters of the antenna array and steering algorithms can be changed using a graphical user interface (GUI).
This paper presents the design and implementation of an ASIC of the Ethernet-ATM bridge which is fabricated in UMC 0.18 mum 1P6M CMOS process. The main function of this chip is to build a bridge between Ethernet and A...
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This paper presents the design and implementation of an ASIC of the Ethernet-ATM bridge which is fabricated in UMC 0.18 mum 1P6M CMOS process. The main function of this chip is to build a bridge between Ethernet and ATM which is not only to merge three chips into a single chip, but also to give up the RISC processor. This development will enhance the broadband network switching ability and stability with small chip size and lower cost. The simulation results present that the gate number, the clock frequency, and the power consumption are 32 kilo-gates, 50 MHz, and 40.2 mW, respectively.
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capabilit...
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ISBN:
(纸本)9781424438273
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processingsystems such as video codecs. As a case study, the demonstration provides the analysis and validation of different software and hardware partitioning of a MPEG-4 simple profile decoder.
With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast cir...
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With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast circuit simulation by GPGPU-LIM (GPGPU-based Latency Insertion Method). First, LIM is reviewed, which is a fast algorithm. Next, implementation of LIM on the general purpose computing on graphic processing unit (GPGPU) is shown. Furthermore, this method is applied to the simulation of power distribution networks (PDNs). Finally, it is confirmed that GPGPU-based LIM is very practical and efficient for the large-scale PDN simulations.
In this paper, we propose a computerized embroidery machine's controller based on ARM and DSP, which divides the whole system into two modules. The main control module based on Samsung S3C2410X, using embedded Lin...
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In this paper, we propose a computerized embroidery machine's controller based on ARM and DSP, which divides the whole system into two modules. The main control module based on Samsung S3C2410X, using embedded Linux as its operating system, is used to analyze the pattern format and run the graphic user interface by using MiniGUI, and the electromechanical control module based on TI TMS320LF2407A is used to control motors, they are connected by a dual-part RAM. We introduce the main software development for the system, design a friendly graphic user interface, and realize high speed data transfer between the two modules. The result indicates that the system accords with the design requirements of a high-end computerized embroidery machine.
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