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45th Midwest Symposium on Circuits and systems (MWSCAS 2002)

作者： Dimitrakopoulos, G Paliouras, V Univ Patras Comp Engn & Informat Dept Patras 26500 Greece

A novel hardware algorithm, architecture and an optimization technique for residue multipliers are introduced in this paper. The proposed architecture exploits certain properties of the bit products to achieve low-complexity implementation via a set of introduced theorems that allow the definition of a graph based design methodology. In addition the proposed multiplier employs the Canonic Signed Digit (CSD) encoding to minimize the number of bit products required to be processed. Performance data reveal that the introduced architecture achieves area x time complexity reduction of up to 55%, when compared to the most efficient previously reported design.

关键词： Digital signal processing

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design and implementation of Turbo Decoders for Software Defined Radio

Design and Implementation of Turbo Decoders for Software Def...

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ieee workshop on signal processing systems (SIPS)

作者： Yuan Lin Scott Mahlke Trevor Mudge Chaitali Chakrabarti Alastair Reid Krisztian Flautner Advanced Computer Architecture Laboratory University of Michigan at Ann Arbor Ann Arbor USA Advanced Computer Architecture Laboratory University of Michigan at Ann Arbor Department of Electrical Engineering Arizona State University USA ARM Ltd. Cambridge United Kingdom

Software defined radio (SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include turbo coding because of its superior performance. However, turbo decoding is computationally intensive, and its low power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2 Mbps decoding throughput

关键词： Decoding Software radio Digital signal processing Computer architecture Wireless application protocol Physical layer Turbo codes Acceleration Processor scheduling Multiaccess communication

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design and implementation of Long-time Coherent Integration Algorithm Based on Multi-core DSP 7

Design and Implementation of Long-time Coherent Integration ...

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2016 ieee Chinese Guidance, Navigation and Control Conference (ieee CGNCC2016)

作者： MA Xian-chao Xi Zheng-hu Wang Jie She Cai-yun Wang Jia Shanghai Radio Equipment Research Institute

ISBN: (纸本)9781467383196

Due to the defects of the long time accumulation method often used now,a new parallel PSO tracking algorithm based on Multi-core Digital signal processing(DSP) parallel system was proposed which greatly reduced the calculation cost and complexity,compensated the target accurately and enhanced the real-time processing.A total of three flights experiment was carried *** time both the conventional10 ms accumulation method and parallel PSO tracking method were adopted to track the target at the same *** experiment results showed that the parallel PSO tracking algorithm was tracking the target with less computable complexity and more effective real-time performance.

关键词： design and implementation of Long-time Coherent Integration Algorithm Based on Multi-core DSP

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A PRML SYSTEM FOR DIGITAL MAGNETIC RECORDING

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ieee JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1992年第1期10卷 38-56页

作者： CIDECIYAN, RD DOLIVO, F HERMANN, R HIRT, W SCHOTT, W Zurich Research Laboratory IBM Research Division Ruschlikon Switzerland

Application of partial-response (PR) signaling and maximum-likelihood sequence detection (MLSD) to digital magnetic recording has been shown in theory and practice to further increase the storage densities and reliability that systems using run-length limited (RLL) coding and peak detection (PD)-still the prevalent signal processing techniques today-can currently achieve. In this paper, the realization of a digital recording system using PR class-IV signaling with MLSD (PRML) is described. To perform MLSD at the high data rates encountered in recording systems, a simple implementation of the Viterbi detector is developed based on a difference-metric algorithm. We present decision-directed schemes for gain control and timing recovery, for tracking variations of the gain and timing phase during data readback, and for fast initial adjustment from a known preamble. The dynamic behavior of the control algorithms is studied by computer simulations. Coding is used to facilitate timing recovery and gain control, to limit the path memory length of the Viterbi detector, and to allow fast and reliable startup of the receiver. The design and properties of rate-8/9 constrained codes are examined. Finally, the problem of equalization is addressed, and analog and combined analog/digital filter implementations are developed. A simple adaptive equalizer capable of compensating variations of the recording channel characteristics with track radius and/or head-to-medium distance is described.

关键词： Gain control maximum likelihood sequence detection Equalization Fasting adaptive equalisers Computer algorithms DIGITAL RECORDING systems path length Gain Data transfer rates

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MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-designed Compressed Neural Networks

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ieee TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND systems 2022年第5期41卷 1550-1562页

作者： Sie, Syuan-Hao Lee, Jye-Luen Chen, Yi-Ren Yeh, Zuo-Wei Li, Zhaofang Lu, Chih-Cheng Hsieh, Chih-Cheng Chang, Meng-Fan Tang, Kea-Tiong Natl Tsing Hua Univ Hsinchu 30013 Taiwan Ind Technol Res Inst Informat & Commun Labs Chutung 31030 Taiwan

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computational cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed on CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computational costs, model compression is a widely studied method to shrink the model size. For implementation in a static random access memory (SRAM) CIM-based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros. In this study, a software and hardware co-design approach is proposed to design MARS, a SRAM-based CIM (SRAM CIM)-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparse CNN, and an SRAM CIM-aware model compression algorithm that considers a CIM architecture to reduce the number of network parameters. With the proposed hardware software co-designed method, MARS can reach over 700 and 400 FPS for CIFAR-10 and CIFAR-100, respectively. In addition, MARS achieves 52.3 and 88.2 TOPs/W in VGG16 and ResNet18, respectively.

关键词： Random access memory Hardware Computer architecture Quantization (signal) Training Common Information Model (computing) Software Compression algorithm computing-in-memory (CIM) deep learning quantization

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FPGA implementation of Wavelet Filters for Power System Harmonics Estimation

FPGA Implementation of Wavelet Filters for Power System Harm...

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International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy systems (ICETEESES)

作者： Tiwari, Vinay K. Jain, Sachin K. Indian Inst Informat Technol Design & Mfg Jabalpur MP India

ISBN: (纸本)9781509021185

In hardware implementation of any signal processing algorithm, computational time and hardware resources are crucial issues. This paper presents design and implementation of a new architecture of wavelet filter for power system harmonics estimation using discrete wavelet packet transform (DWPT). Usually, DWPT provides coefficients as the output, however, the proposed architecture also includes provision for providing rms values directly. The proposed method reduces computational requirements and save memory resources. Xilinx system generator, a higher abstraction level tool, has been used to simulate and implement the proposed scheme on the Xilinx Artix-7 FPGA AC-701 board. Performance of the proposed architecture has been validated and compared through hardware co-simulation with variety of synthetic and experimental signals.

关键词： Discrete Wavelet Packet Transform (DWPT) Field Programming Gate Array (FPGA) Finite Impulse Response (FIR) Filter Power Quality Xilinx System Generator (XSG)

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A sub-10mW real-Time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC 7

A sub-10mW real-Time implementation for EMG hand gesture rec...

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7th International workshop on Advances in Sensors and Interfaces, IWASI 2017

作者： Benatti, Simone Rovere, Giovanni Bosser, Jonathan Montagna, Fabio Farella, Elisabetta Glaser, Horian Schonle, Philipp Burger, Thomas Fateh, Schekeb Huang, Qiuting Benini, Luca DEI University of Bologna Italy Integrated System Laboratory ETH Zurich Zurich8092 Switzerland ICT Center-FBK Trento Italy

ISBN: (纸本)9781509067060

Real-Time biosignal classification in power-constrained embedded applications is a key step in designing portable e-healtb devices requiring hardware integration along with concurrent signal processing. This paper presents an application based on a novel biomedical System-On-Chip (SoC) for signal acquisition and processing combining a homogeneous multi-core cluster with a versatile bio-potential front-end. The presented implementation acquires raw EMG signals from 3 passive gel-electrodes and classifies 3 hand gestures using a Support Vector Machine (SVM) pattern recognition algorithm. Performance matches state-of-The-Art high-end systems both in terms of recognition accuracy (>S5%) and of real-Time execution (gesture recognition time 300 ms). The power consumption of the employed biomedical SoC is below 10 mW, outperforming implementations on conunercial MCUs by a factor of 10, ensuring a battery life of up to 160 hours with a common Li-ion 1600 mAh battery. © 2017 ieee.

关键词： System-on-chip

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A system for real-time synthesis of subtle expressivity for life-like MPEG-4 based virtual characters

A system for real-time synthesis of subtle expressivity for ...

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2004 ieee 6th workshop on Multimedia signal processing

作者： Bonamico, Carlo Braccini, Carlo Lavagetto, Fabio Costa, Maurizio DIST University of Geneva Via Opera Pia 13 Genova Italy Eptamedia S.r.l. Via Canepari 20A/5 Genova Italy

ISBN: (纸本)0780385780

Non-verbal behaviors have a key role in making a Virtual Character appear life-like. We describe an extensible system for the specification, control and real-time generation of facial expressions and gestures. The system approximates in a MPEG-4 based Virtual Character the wide expressive range, dynamism (an expression's meaning significantly depends on its temporal evolution) and variability (an emotion is never expressed exactly in the same way by different people, and even by the same person at different times), typical of human non-verbal behavior. The MPEG-4 standard only allows high-level control of 6 basic emotions, and does not explicitly support the description of an expression temporal evolution. Our approach has been that of creating a hierarchical model of expressiveness;expressions are defined in term of parameterized functions controlling low-level animation parameters trajectories (by means of an XML-based Expression Definition Markup Language). The real-time generation of those expressions is performed by an Expression Synthesis Engine. The system allows to effectively modulate expressivity both at design-time (the developer tweaks the parameters to give the character a given expressive style), and at run-time (the engine automatically changes the way in which an expression is performed each time), producing controllable, but non-deterministic, behavior patterns, a key factor for enhancing believability.

关键词： Real time systems

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Unconventional signal processing architecture for reconfigurable on-chip communication systems 6

Unconventional signal processing architecture for reconfigur...

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6th ieee Latin American Symposium on Circuits and systems, LASCAS 2015

作者： Vazquez-Avila, J.L. Sandoval-Arechiga, R. Gea-Garcia, B.I. Parra-Michel, R. Mario-Siller CINVESTAV-IPN Guadalajara Unit Mexico

ISBN: (纸本)9781479983322

Algorithms for digital communication systems can be represented via a set of specialized signal processing (SP) blocks. Hence, in the implementation of these algorithms, the interconnection among the processing blocks aggregates complexity to the design. Usually, these interconnections are made through specialized glue logic, Point-to-Point (P2P) interconnections, Bus or a Network on Chip (NoC). Furthermore, the communications industry's trend is to move forward to Software Defined Radio (SDR) or reconfigurable communications SoC, which imposes hard constrains in the selected interconnection approach. Particularly, the management tasks directly influence the system's performance. Therefore, it is important to study the decision of leaving this administration to a dedicated processor or to a general purpose processor. Here, a NoC-based architecture is proposed to overcome the management problem. A Feeder-Collector, that takes out the reconfiguration and managerial tasks from the main CPU is introduced. This architecture creates a HW-based library of SP functions which simplifies software applications, without sacrificing performance. Analytical and simulation results show that our proposal achieves a high performance and the lowest CPU's load compared with P2P, Bus and conventional NoC interconnections. © 2015 ieee.

关键词： signal processing

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design and implementation of a fiber optic perimeter intrusion detection system 13

Design and implementation of a fiber optic perimeter intrusi...

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13th International Bhurban Conference on Applied Sciences and Technology (IBCAST)

作者： Qadeer, M. A. Islam, Javaid Rizvi, S. Arif, Usman Ctr Excellence Sci & Appl Technol Islamabad Pakistan

ISBN: (纸本)9781467391276

This paper explains the design of a real time fiber optic intrusion sensing system. The said system operates passively on the field, unlike most of its counterparts, without any performance compromise. Optical signal processing and electronics is discussed. Simulation results are included in order to support the design. signal estimation is accomplished through novel stochastic estimation technique. The POD of the system is found to be greater than 90% through extensive testing.

关键词： Beam splitter (BS) Fiber optic sensors (FOS) Perimeter intrusion detection systems (PIDS) Probability of detection (POD)

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