A new architectural technique to reduce energy dissipation of frame memory is proposed. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit...
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A new architectural technique to reduce energy dissipation of frame memory is proposed. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit-width to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The method is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulation results show that using this method we can reduce the total energy consumption of frame memory by 20% without affecting the picture quality.
In this paper we present an embedded high performance Serial RapidIO TM data acquisition interface for Silicon Retina technology based computer vision applications. The Silicon Retina technology is a new kind of bio-i...
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The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. The energy limitations ...
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The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. The energy limitations of mobile appliances create the demand for low-power implementations. We propose a custom high-performance MPEG-4 video encoder. The fully dedicated video pipeline is realized using a systematic design approach and exploits the inherent functional parallelism of the compression algorithm. Memory optimizations and algorithmic optimizations combined at the high-level and their effect on the power-efficiency is demonstrated. The resulting MPEG-4 video encoder contains a tailored memory hierarchy; uses burst oriented accesses to external memory and supports real-time processing of 30 4CIF frames per second while only consuming 71 mW in a 180 nm, 1.62 V UMC technology.
Coping with the complexity of future energy grids and the rising challenges of the energy transition to more renewable energy sources (RES), an Energy Hub Gas (EHG) concept appears to be a promising approach. This con...
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ISBN:
(纸本)9781450386081
Coping with the complexity of future energy grids and the rising challenges of the energy transition to more renewable energy sources (RES), an Energy Hub Gas (EHG) concept appears to be a promising approach. This concept combines various technical components to a sector-coupling system network to support the electricity grid with ancillary and balancing services to cope with the fluctuating generation by RES and to provide (renewable) energy carriers. Additionally, the EHG serves as regional gateway and as a converter for large, centralized RES-feed-in and aggregation/distribution hub of local RES-feed-in. For combining several separate models from different domains to an EHG system model, a co-simulation approach is used with high regard on flexibility concerning the modelling aspects as well as high modularity to easily adapt the concept to further use cases. As main results presented in the paper, the coherence of the extended EHG system model and its usability for implementation in co-simulation can be shown in first simulations.
Gaze awareness and eye contact serve important functions in social interaction. In order to maintain those functions in 2D and 3D videoconferencing systems, human sensitivity to eye contact and gaze direction needs to...
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As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This process...
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As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications. Moreover, densely encoded instructions supporting memory operands, DSP-like addressing modes, and SIMD capability boost the performance while keeping the code size and hardware cost small. To maximally utilize this architecture, a software environment including a code converter, a VLIW compiler system, and a compiled simulator has also been developed. The processor core has been synthesized for LSI logic 0.25 μm library, which results in the total gate count of 102 K. In spite of the relatively smaller issue rate, the proposed processor shows a comparable or higher performance in terms of both the cycle count and the code size when compared to the 8-issue TMS320C62xx, for DSP benchmark kernels and an H.263 video encoder.
At present, the archives management of enterprises is facing great work pressure, mainly focusing on data sharing and information operation. This paper mainly studies the application of blockchain technology, and expl...
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The actual and next communication schemes tend to use OFDM systems in order to provide high baud rates and less inter symbol interference. Some examples are 802.11, 802.16, MC-CDMA, Digital Video Broadcasting, Wireles...
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ISBN:
(纸本)0780392302
The actual and next communication schemes tend to use OFDM systems in order to provide high baud rates and less inter symbol interference. Some examples are 802.11, 802.16, MC-CDMA, Digital Video Broadcasting, Wireless USB or Wireless Firewire among others. Trying to provide a solution to the new devices emerging, slow standard adoption, poor spectrum use, etc. Joe Mitola introduced the concept of "Software Defined Radio", which involves exhaustive configurable digital signalprocessing like FTT, therefore FPGAs could support many of its operations. This work presents a FPGA design, validation and implementation of an "Orthogonal Frequency Division Multiplexing" (OFDM) modulator for ieeeF 802.11a using a high level design tool, also reports the resources requirements for the presented system.
A systematic approach to design two families of multiplierless approximations of the DCT with the lifting scheme is presented, based on Chen's and Loeffler's factorizations of the DCT matric, respectively. The...
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ISBN:
(纸本)0780365143
A systematic approach to design two families of multiplierless approximations of the DCT with the lifting scheme is presented, based on Chen's and Loeffler's factorizations of the DCT matric, respectively. The analytical values of all the lifting steps are derived, which can be approximated by dyadic values to enable fast implementations with only shifts and additions. Different trade-offs between the complexity and the performance can be easily obtained A scaled lifting structure is proposed to further reduce its complexity. The performance of the lifting-based DCT implementation is demonstrated in the frameworks of JPEG and H.263+. Besides, lossless compression capability is also presented.
The BER performance of imperfect matched filter (IMF) is compared to the BER performance of transmit reference (TR) receiver in a typical office multi-user scenario assuming LOS/NLOS conditions for terminals. Due to t...
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ISBN:
(纸本)0780383737
The BER performance of imperfect matched filter (IMF) is compared to the BER performance of transmit reference (TR) receiver in a typical office multi-user scenario assuming LOS/NLOS conditions for terminals. Due to the extremely high processing requirements of the matched filter, it is assumed that for an implementation the number of bits as well as the number of filter coefficients for the correlation template signal representation has to be as low as possible introducing implementation loss. Further imperfect channel estimation is taken into account. The resulting BER performance of IMF receiver is compared to the BER performance of TR receiver, which has been modified compared to original concept with regards to a) time gating, i.e. integration is just performed in the time interval where significant pulse energy is received, b) 2PAM/M-PPM modulation, and c) optional reference pulse averaging. Results show, that both receiver types can reach the uncoded target BER of 10(-2) in all environments investigated. However the IMF receiver outperforms the TR receiver by about 3 dB in LOS and by about 7 dB in NLOS. For the IMF receiver the required E-b/N-0 ratio to achieve the target BER strongly depends on the number of filter coefficients. More details can be found in the final deliverable of the UWB work package of the European research project *** [1].
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