The objective of the hArtes (holistic approach to reconfigurable real time embedded systems) is to provide a tool set that facilitates the management of entire design flow. Despite of its improved design productivity,...
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The objective of the hArtes (holistic approach to reconfigurable real time embedded systems) is to provide a tool set that facilitates the management of entire design flow. Despite of its improved design productivity, the two bottleneck are: (1) capturing initial application specifications in the specified graphical tool and (2) Cycle accurate performance estimation in design space exploration. We propose: (1) a transformation methodology for converting reference sequential C code to data-flow specifications and (2) a design space exploration framework based on cycle accurate performance estimation. The proposed transformation methodology is based on functions reorganization and variables definitions. The proposed design space exploration framework consists of two design loops: computational architecture selection loop and communication architecture selection loop. Before entering into these loops, it is critical to estimate the performance of application function blocks. We propose a performance estimation methodology by performing simulations at CABA (cycle accurate bit accurate) level. Instead of simulating the entire application, each function block is instrumented and executed on the target simulation platform and the resulting information is stored in a performance estimation library. Experimentation with H.264 video encoding application proves the viability of the proposed transformation methodology. Validation and performance evaluations for performance estimation technique are done by extending the SoCLib library of simulation models.
Distribution of multimedia content through the internet has gain popularity with the advancement of multimedia technology through software application with different transmission capabilities. Current conventional sys...
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Distribution of multimedia content through the internet has gain popularity with the advancement of multimedia technology through software application with different transmission capabilities. Current conventional system implementation works perfectly for a guaranteed network bandwidth. However, when the packet experience losses due to drop in bandwidth, it could not preserve an acceptable video quality over the heterogeneous network. Thus, if the bandwidth could be determined in real-time, an application that controls the scalability of video stream sent over the channel can be used to control the video quality. This is done by reducing the bit-rate of the video to be sent according to current available bandwidth. In this paper, a scalable video streaming system with automate bandwidth control over heterogeneous network, using spatial scalability approach and end-to-end available bandwidth estimation are designed and implemented. Distribution of multimedia data streaming would be improved without any jitter and could fit to any devices with various performance capabilities.
This paper presents the plan of action for a research project that is in the early stages of investigating social interaction in a group improvisation and reflecting the results in its implementation. The research pur...
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This paper presents the plan of action for a research project that is in the early stages of investigating social interaction in a group improvisation and reflecting the results in its implementation. The research purports the design of an interactive performance system that enables audience participation in an improvisational mobile music performance. The main emphasis of the research is to understand more about social behavior in collective music making processes through audience-participants' gestures in the moment of playing. Group improvisation shifts interaction and participatory behavior into a social level. The role of the audience is critical, not only for the design process of the research, but also for the experience of such an experimental music.
A general method for analogue implementation of high-frequency wavelet transform is proposed in which the wavelet transform is synthesized by a bank of Gm-C bandpass filters whose impulse responses are the mother wave...
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ISBN:
(纸本)9781424444793;9781424444809
A general method for analogue implementation of high-frequency wavelet transform is proposed in which the wavelet transform is synthesized by a bank of Gm-C bandpass filters whose impulse responses are the mother wavelet and its dilations. The proposed approach employs the inverse follow-the-leader-feedback multiple loop feedback structure for filter design to lower the magnitude sensitivity and facilitate the arbitrary rational function realization. The Marr wavelet is used as an example in this paper to illustrate design details. The wavelet filter is simulated using TSMC 1.8V 0.18mum CMOS technology. Simulation results show performance values obtained.
The design and the implementation of a portable GNSS baseband logging system which can log raw GPS L1 baseband more than one hour or longer is presented. In addition, the design covers GPS (L1, L2)/GLONASS/Galileo/Com...
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The design and the implementation of a portable GNSS baseband logging system which can log raw GPS L1 baseband more than one hour or longer is presented. In addition, the design covers GPS (L1, L2)/GLONASS/Galileo/Compass frequency and the maximal sample frequency is about 50 *** system is based on Blackfin DSP and uses CompactFlash card for storage. The data is extracted by reading the CompactFlash card to store as a data file. The recorded data file is analyzed by using the FFT to acquire the GPS satellites signals and the position is calculated by using the open source GPS positioning software. The system is very portable because of the CF+DSP design and can also be used on missile and satellite. It provides a good research and development platform for the GNSS software receiver.
The implementation of the S-APAS (Scalable Multifunction Radio Frequency - Active Phased Array System) concept requires the use of autonomous T/R modules connected to a common digital bus. The T/R modules have the fun...
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The implementation of the S-APAS (Scalable Multifunction Radio Frequency - Active Phased Array System) concept requires the use of autonomous T/R modules connected to a common digital bus. The T/R modules have the functions of radiating energy in the radar space, collecting the relative returns and exchanging data and commands with the processing/control blocks. The technological aspects related to producing a T/R module, that is flexible and cheap enough to be used in different radar systems, at least within the same operating band, have been analyzed in previous papers. Further aspects derived from the S-APAS architectural concept have been considered here, in order to find the right intercepts with available technologies and with new technologies under development. In particular, the transmitter performance, the bus throughput and the performance of the data/ signalprocessing blocks are among the most critical items, to be analyzed carefully. This paper defines the dimensioning criteria for the proposed architecture in a number of cases related to different applications at different operating frequencies, defines the basic design principles and discusses the results, with respect to the above parameters, in order to find the technological constraints related to the physical implementation of the S-APAS architectural concept. The study is limited to applications with operating frequencies ranging from L band to X band, but the results can be easily extended to other frequencies of interest.
Rapid advances in integrated circuit (IC) development predicted by Moore's Law lead to increasingly complex, hard to verify IC designs. design insiders or adversaries employed at untrusted locations can insert mal...
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Rapid advances in integrated circuit (IC) development predicted by Moore's Law lead to increasingly complex, hard to verify IC designs. design insiders or adversaries employed at untrusted locations can insert malicious Trojan circuits capable of launching attacks in hardware or supporting software-based attacks. In this paper, we provide a method for detecting Trojan circuit denial-of-service attacks using a simple, verifiable hardware guard external to the complex CPU. The operating system produces liveness checks, embedded in the software clock, to which the guard can respond. We also present a novel method for the OS to detect a hardware-software (HW/SW) Trojan privilege escalation attack by using OS-generated checks to test if the CPU hardware is enforcing memory protection (MP). Our implementation of fine-grained periodic checking of MP enforcement incurs only 2.2% overhead using SPECint 2006.
This paper presents a new architecture and circuit implementation of 1-D median filter. The proposed circuit belongs to the class of non-recursive sorting network architectures that process the input samples sequentia...
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ISBN:
(纸本)9781424444793;9781424444809
This paper presents a new architecture and circuit implementation of 1-D median filter. The proposed circuit belongs to the class of non-recursive sorting network architectures that process the input samples sequentially in the word-based manner. In comparison to the related schemes, it maintains sorting of samples from the previous position of the sliding window, positioning only the incoming sample to the correct rank. Unlike existing 1-D filter implementations, the circuit has linear hardware complexity, minimal latency and achieves throughput of 1/2 of the sampling rate. Experimental evaluation and comparisons show high efficiency of our design.
This paper addresses the design of a high-speed motor bus transfer system for power generating plants and industrial facilities where motor loads require comprehensive source transfer strategies during transfer of the...
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ISBN:
(纸本)9781424433988;9781424433995
This paper addresses the design of a high-speed motor bus transfer system for power generating plants and industrial facilities where motor loads require comprehensive source transfer strategies during transfer of the load from one source to another source. Motor bus transfer schemes are needed not only to maintain process continuity but also to transfer sources in such a manner to prevent damage to the motors and connected loads. The motor bus frequency and voltage decay rapidly upon disconnection from the main source. This paper proposes a digital signalprocessing algorithm which can measure the magnitude and phase angle of the decaying bus voltage accurately, while measuring the auxiliary source voltage magnitude and phase angle at rated frequency. The paper details an algorithm to predict the phase coincidence between the motor bus voltage and the auxiliary source voltage. The algorithm uses delta frequency, the rate of change of delta frequency and breaker closing time to predict the phase coincidence. The paper also details the implementation of the motor bus transfer scheme which includes fast, in-phase and residual transfer methods. Results of some real-time transfer cases are also included.
Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. T...
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Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to try to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge from that field of work and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented proving that this approach has a great potential.
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