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2014 29th Conference on design of Circuits and Integrated systems, DCIS 2014

作者： Rossello, J.L. Canals, V. Oliver, A. Alomar, M. Morro, A. Department of Physics University of Balearic Islands Palma of Majorca07122 Spain

ISBN: (纸本)9781479957439

In this work we show a study about which processes are related to chaotic and synchronized neural states based on the study of in-silico implementation of Stochastic Spiking Neural Networks (SSNN). Chaotic neural ensembles are excellent transmission and convolution systems. At the same time, synchronized cells (that can be understood as ordered states of the brain) are associated to more complex non-linear computations. We experimentally show that complex and quick pattern recognition processes arise when both synchronized and chaotic states are mixed. These measurements are in accordance with in-vivo observations related to the role of neural synchrony in pattern recognition and to the speed of the real biological process. The measurements obtained from the hardware implementation of different types of neural systems suggest that the brain processing can be governed by the superposition of these two complementary states with complementary functionalities (non-linear processing for synchronized states and information convolution and parallelization for chaotic). © 2014 ieee.

关键词： Neural networks

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Optimal design and parallel implementation of variable FIR filters with tuneable magnitude and non-integer phase-delay 1

Optimal design and parallel implementation of variable FIR f...

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1st ieee International Conference on Circuits and systems for Communications

作者： Deng, TB Okamoto, E Toho Univ Fac Sci Dept Informat Sci Chiba 2748510 Japan

ISBN: (纸本)5742202601

This paper proposes a weighted least-squares (WLS) method for designing variable one-dimensional (1-D) FIR digital filters with simultaneously variable magnitude and variable non-integer phase-delay responses. First, the coefficients of a variable FIR filter Are represented as the two-dimensional (2-D) polynomials of a pair of spectral parameters;one is for tuning the magnitude response, and the other is for varying its non-integer phase-delay response. Then the optimal coefficients of the 2-D polynomials are found by minimizing the total weighted squared error of the variable frequency response. Finally, we show that the resulting variable FIR filter can be implemented in a parallel form, which is suitable for high-speed signal processing.

关键词： variable filter magnitude and phase-delay

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Least squares predictive transform space-time array processing for airborne MTI radar

Least squares predictive transform space-time array processi...

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1992 ieee Long Island Section Adaptive Antenna systems Symposium, AASS 1992

作者： Guerci, J.R. Feria, E.H. Grumman Corporation Corporate Research Center Signal Processing Laboratory BethpageNY11714 United States Department of Applied Sciences City University of New York College of Staten Island Staten IslandNY10301 United States

A novel space-time array processing strategy for adaptive airborne MTI radar is presented via the application of a multichannel least squares predictive transform (PT) signal modeling procedure. The crux of the technique is the utilization of a multichannel adaptive "whitening" filter, obtained from a least squares PT signal modeling procedure, which attempts to "pre-whiten" the otherwise angledoppler correlated clutter signal prior to detection. As with previous PT applications, such as in coding and estimation, the synergistic effect of the prediction and transformation mechanisms provide additional means for reducing both design and implementation complexity while gradually trading off performance-as measured by the degree of clutter cancellation for the application considered herein. In addition to a background discussion of the PT modeling procedure, simulation results are presented which demonstrate the utility of the approach in a adaptive airborne MTI radar employing an eight element phased array antenna operating in Rayleigh distributed clutter. © 1992 by'Institute of Electrical And Electronics Engineers, Inc.

关键词： Array processing

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DSP-based real-time control systems design, analysis, and implementation for reinforcement of controls education

DSP-based real-time control systems design, analysis, and im...

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113th Annual ASEE Conference and Exposition, 2006

作者： Rubaai, Ahmed Johnson, James Howard University United States Howard University Washington DC United States Department of Electrical Engineering United States IEEE United States United States IEEE IAS Manufacturing Systems Development and Applications Department United States IAS Executive Board United States Department of Civil Engineering College of Engineering Architecture and Computer Sciences Howard University United States

This article describes the development, implementation, and demonstration of a real-time laboratory platform for use in an undergraduate laboratory control course. The design, analysis, and implementation stages are carried out entirely using a dSPACE DS1104 digital signal processor (DSP)-based real-time data acquisition control (DAC) system and MATLAB/Simulink software tools. The control law is designed in Simulink and executed in real-time using the dSPACE DS 1104 DSP-board. Once the controller has been built in Simulink, the MATLAB Real-Time workshop (RTW) routine is used to automatically convert the Simulink block-set to a machine code that runs on the DS1 104 DSP processor. While an experiment is running, the dSPACE DS1104 provides a mechanism that allows the student to change controller parameters online. Thus, it is possible for students to view the real process while the experiment is in progress. Students are encouraged to compare their designs with those of other students. Students are enthusiastic about the lab;and, their comments are positive. © American Society for Engineering Education, 2006.

关键词： Digital signal processors

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Robust Secrecy Energy Efficient Beamforming in MISOME-SWIPT systems With Proportional Fairness

Robust Secrecy Energy Efficient Beamforming in MISOME-SWIPT ...

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ieee Global Conference on Communications (GLOBECOM) / workshop on Wireless Networking and Control for UAV

作者： Dong, Yanjie Hossain, Md. Jahangir Cheng, Julian Leung, Victor C. M. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada Univ British Columbia Sch Engn Kelowna BC Canada

ISBN: (纸本)9781538647271

The joint design of beamforming vector and artificial noise covariance matrix is investigated for multiple-input-singleoutput-multiple-eavesdropper simultaneous wireless information and power transferring (MISOME-SWIPT) systems. A secrecy energy efficiency (SEE) maximization problem is formulated in the MISOME-SWIPT system with imperfect channel state information and proportional secrecy rate constraints. Since the formulated SEE maximization problem is non-convex, it is first recast into a series of convex problems in order to obtain the optimal solution with a reasonable computational complexity. Numerical results are used to verify the performance of the proposed algorithm and to reveal practical insights.

关键词： Optimization Wireless communication Power demand Array signal processing Energy harvesting MIMO communication Channel estimation

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EeteS-The EnMAP End-to-End Simulation Tool

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ieee JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2012年第2期5卷 522-530页

作者： Segl, Karl Guanter, Luis Rogass, Christian Kuester, Theres Roessner, Sigrid Kaufmann, Hermann Sang, Bernhard Mogulsky, Valery Hofer, Stefan Deutsch GeoForschungsZentrum GFZ Helmholtz Zentrum Potsdam Remote Sensing Sect D-14473 Potsdam Germany Univ Oxford Clarendon Lab Dept Atmospher Ocean & Planetary Phys Oxford OX1 3PU England Univ Oxford Atmospher Ocean & Planetary Phys Subdept Oxford England Kayser Threde GmbH D-81379 Munich Germany

The design of future Earth imaging systems, the optimization of fundamental instrument parameters, and the development and evaluation of data pre-processing and scientific-exploitation algorithms require an accurate end-to-end simulation of the entire image generation and processing chain. For this purpose, the end-to-end simulation software EeteS has been developed within the framework of the Environmental Mapping and Analysis Program (EnMAP) mission. This paper presents the EeteS simulation approach and software implementation focusing on calibration and pre-processing. The sequential processing chain of the EnMAP scene simulator consists of four independent parts-the atmospheric, spatial, spectral and radiometric modules. This forward simulator is coupled with a backward simulation branch consisting of calibration modules (non-linearity, dark current and absolute radiometric calibration) and a series of pre-processing modules (radiometric calibration, co-registration, atmospheric correction and orthorectification) forming the complete end-to-end simulation tool. In the result EeteS is capable of simulating EnMAP-like raw image scenes (L0) taking into account a variety of instrumental and environmental configurations. Furthermore, EeteS allows simulations of EnMAP reflectance images carrying out the complete L1 and L2 processing chains. Analysis of the intermediate and final EeteS simulation products has shown the accurate, reliable and consistent performance of the developed modules enabling the system to support technical decision-making processes required for the development of the EnMAP sensor. EeteS has also been used to estimate the SNR characteristics of potential EnMAP products after calibration and pre-processing. Comparing the results to SNR characteristics achieved by the already existing EO-1 Hyperion system has shown a significantly improved SNR which can be expected from future EnMAP data products.

关键词： End-to-end simulation EnMAP image pre-processing sensor calibration signal-to-noise ratio

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designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Designing dynamically reconfigurable SoCs: From UML MARTE mo...

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2010 Conference on design and Architectures for signal and Image processing, DASIP2010

作者： Quadri, Imran Rafiq Meftali, Samy Dekeyser, Jean-Luc INRIA LILLE NORD EUROPE LIFL University of Lille Lille France

ISBN: (纸本)9781424487356

Due to continuous hardware/software evolution related to systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of Model-Driven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs. © 2010 ieee.

关键词： Integrated circuit design

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High-throughput LDPC decoding using the RHS algorithm

High-throughput LDPC decoding using the RHS algorithm

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6th Annual Conference on design and Architectures for signal and Image processing, DASIP 2012

作者： Leduc-Primeau, Francois Raymond, Alexandre J. Giard, Pascal Cushon, Kevin Thibeault, Claude Gross, Warren J. Department of Electrical and Computer Engineering McGill University Montreal QC H3A 0E9 Canada Department of Electrical Engineering École de Technologie Supérieure Montreal QC H3C 1K3 Canada

ISBN: (纸本)9782953998726

The relaxed half-stochastic (RHS) algorithm is a recently proposed binary message-passing decoding algorithm for low-density parity check codes that can reach the same error rate performance as belief propagation algorithms that exchange LLR messages. Because of its low-complexity interleaver, the RHS algorithm makes it possible to achieve a fully-parallel implementation that can converge to a codeword in only a few clock cycles on average, enabling high throughput and power efficiency. To demonstrate the practicality of the RHS algorithm, we implement a decoder for the popular ieee 802.3an 10GBASE-T standard. The paper presents details of the hardware implementation, as well as post-layout results for an ASIC implementation in 65nm CMOS technology, which indicate that the decoder can operate at 448 MHz and occupies an area of 4.41 mm2. The results obtained from bit-accurate software simulations show that the decoder meets the latency requirement prescribed by the standard and provides an average throughput of 160 Gbps. © 2012 ECSI.

关键词： Stochastic systems

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FPGA-based Real Time Embedded Hough Transform Architecture for circles detection 12

FPGA-based Real Time Embedded Hough Transform Architecture f...

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12th Conference on design and Architectures for signal and Image processing (DASIP)

作者： Chuquimia, Orlando Pinna, Andrea Marsala, Christophe Dray, Xavier Bertrand, Granado Sorbonne Univ CNRS LIP6 UMR 7606 Paris France Sorbonne Univ Hop St Antoine AP HP Paris France

ISBN: (纸本)9781538682371

Hough Transform is a widely used shapebased algorithm for object detection and localization [6], this technique can be generalized to parametric curves as circles. For a real time execution and embedded integration, several optimizations are necessary due to the large memory and computational requirements. This paper presents an efficient real-time pipelined architecture with a FPGA implementation of our Hough Transform for multi-circles detection. The computation of center candidates was improved. A three stages pipeline architecture was designed in order to reduce the processing latency and cadence. The architecture has been integrated into a Xilinx Zynq-7000 XC7Z020 containing a FPGA Artix-7. The global system uses 78.5 BRAMs, 153 DSP slices, 21638 LUTs. Our global system can support a maximum clock frequency of 128.89 MHz. We validate our architecture using a 125MHz clock frequency and we obtain a latency of 33.214 ms and an interval between two images of 16,607 ms for a 1920x1080 pixels image. According to our results, our architecture offer a throughput more than 4 times better than the faster state of the art architecture.

关键词： Transforms Histograms Computer architecture Field programmable gate arrays Image edge detection Real-time systems Hardware

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Towards a bio-inspired mixed-signal retinal processor

Towards a bio-inspired mixed-signal retinal processor

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2004 ieee International Symposium on Circuits and systems - Proceedings

作者： Constandinou, Timothy G. Georgiou, Julius Toumazou, Chris EEE Dept. Imp. Coll. of Sci. Technol./Med. London SW7 2BT United Kingdom Toumaz Technology Limited Culham Science Centre Abington Oxfordshire OX14 3DB United Kingdom Geosilicon Limited 7 Thessalonikis Avenue Strovolos Nicosia 2020 Cyprus

A robust distributed architecture for real-time object-based processing is presented for tasks such as object size, centre and count determination. This approach uses the input image to enclose a feedback loop to realize a data-driven pulsating action. Outlined is the top level design for hardware implementation in a standard CMOS technology.

关键词： Real time systems

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