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5th International Conference on Inventive Computation Technologies (ICICT)

作者： Priya, Shanmuga N. Radha, N. K Ramakrishnan Coll Engn ECE Dept Trichy India

ISBN: (纸本)9781728146850

Addition is a basic component for any operation commonly used in many VLSI systems, such as implementation-specific digital signal processing (DSP) and integrated circuit architecture. Another two important criteria for the design of complete adders would be power consumption and rpm. Full adder architecture with low power consumption and fast latency of more transmission is of great concern in the implementation of modern digital systems. To achieve maximum architecture trade-offs, power delay device or energy consumption per process was added. Digital circuit performance can be optimized through proper logic style selection. In this paper, we design an extended multiplier low power consumption adders to minimize complexity and reduce power consumption compared to other designs. This can increase the speed and reduce the dissipation of power. A newer GDI (Gate Diffusion Input) transmission gate was used to implement the adder configuration. This technology allows reducing the power consumption, delay and area of low-power digital circuits thus dealing with low logic design difficulties.

关键词： VLSI DSP GDI Low power Full adder CMOS Power delay Multiplier

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EeteS-The EnMAP End-to-End Simulation Tool

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ieee JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2012年第2期5卷 522-530页

作者： Segl, Karl Guanter, Luis Rogass, Christian Kuester, Theres Roessner, Sigrid Kaufmann, Hermann Sang, Bernhard Mogulsky, Valery Hofer, Stefan Deutsch GeoForschungsZentrum GFZ Helmholtz Zentrum Potsdam Remote Sensing Sect D-14473 Potsdam Germany Univ Oxford Clarendon Lab Dept Atmospher Ocean & Planetary Phys Oxford OX1 3PU England Univ Oxford Atmospher Ocean & Planetary Phys Subdept Oxford England Kayser Threde GmbH D-81379 Munich Germany

The design of future Earth imaging systems, the optimization of fundamental instrument parameters, and the development and evaluation of data pre-processing and scientific-exploitation algorithms require an accurate end-to-end simulation of the entire image generation and processing chain. For this purpose, the end-to-end simulation software EeteS has been developed within the framework of the Environmental Mapping and Analysis Program (EnMAP) mission. This paper presents the EeteS simulation approach and software implementation focusing on calibration and pre-processing. The sequential processing chain of the EnMAP scene simulator consists of four independent parts-the atmospheric, spatial, spectral and radiometric modules. This forward simulator is coupled with a backward simulation branch consisting of calibration modules (non-linearity, dark current and absolute radiometric calibration) and a series of pre-processing modules (radiometric calibration, co-registration, atmospheric correction and orthorectification) forming the complete end-to-end simulation tool. In the result EeteS is capable of simulating EnMAP-like raw image scenes (L0) taking into account a variety of instrumental and environmental configurations. Furthermore, EeteS allows simulations of EnMAP reflectance images carrying out the complete L1 and L2 processing chains. Analysis of the intermediate and final EeteS simulation products has shown the accurate, reliable and consistent performance of the developed modules enabling the system to support technical decision-making processes required for the development of the EnMAP sensor. EeteS has also been used to estimate the SNR characteristics of potential EnMAP products after calibration and pre-processing. Comparing the results to SNR characteristics achieved by the already existing EO-1 Hyperion system has shown a significantly improved SNR which can be expected from future EnMAP data products.

关键词： End-to-end simulation EnMAP image pre-processing sensor calibration signal-to-noise ratio

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DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

DESDynI Quad First Stage Processor - A Four Channel Digitize...

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ieee Aerospace Conference

作者： Chuang, Chung-Lun Shaffer, Scott Smythe, Robert Niamsuwan, Noppasin Li, Samuel Liao, Eric Lim, Chester Morfopolous, Arin Veilleux, Louise CALTECH Jet Prop Lab Pasadena CA 91109 USA

ISBN: (纸本)9781467318112

The proposed Deformation, Eco-systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

关键词： analogue-digital conversion array signal processing radar signal processing synthetic aperture radar

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Modeling and optimization of buffering trade-offs for hardware implementation of image processing applications

Modeling and optimization of buffering trade-offs for hardwa...

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ieee workshop on signal processing systems (SIPS)

作者： Dong-Ik Ko S.S. Bhattacharyya Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies University of Maryland College Park USA

As modern image and video processing applications handle increasingly higher image resolutions, the buffering requirements between communicating functional modules increase correspondingly. The performance and cost of these applications can change dramatically depending on the implementation methods for FIFO buffers and the data delivery methods between modules. This paper introduces a new FIFO hardware mapping algorithm based on pointer-based token delivery from dataflow semantics for image and video processing applications. This approach significantly improves the performance of dataflow based implementation of image and video processing systems, and allows effective prediction of changes in performance and buffer memory requirements associated with changes in image resolution. Our pointer-based token delivery method allows indirect token delivery between actors by pointers in conjunction with use of a shared memory. Each pointer references a data block stored in the shared memory. In pointer-based token delivery, a buffer can be configured to be implemented as the combination of a small, fast FIFO and a larger, relatively cheap shared memory while providing an attractive trade-off between performance and hardware cost. We present the complete semantics of our pointer-based modeling method, systematic techniques for mapping representations using these semantics into efficient implementations, and experimental results that demonstrate the performance of the proposed pointer-based techniques.

关键词： Hardware Image processing Application software Costs Field programmable gate arrays Image resolution signal processing algorithms Educational institutions Video sharing Digital signal processing

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design and implementation of Number Plate Recognition System Based on Cortex-M3 3

Design and Implementation of Number Plate Recognition System...

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3rd ieee International Conference on Information systems and Computer Aided Education, ICISCAE 2020

作者： Wang, Chenyang Ji, Huaikun Zhang, Yuxiao Liu, Changkun Hefei University of Technology Hefei China

ISBN: (纸本)9781728183039

This design is based on the FPGA platform and builds an automatic number plate recognition system with an on-chip Cortex-M3 core, and collects the number plate photo through the OV5640 camera, and converts it into a digital signal for the image processing module. The image processing module can obtain a clear binary image after gray-scale processing, binarization processing and median filtering. Then it determines the position and character information of the number through vertical and horizontal projection and numerical recognition. The numerical result obtained by the recognition is input to Cortex-M3 through the AHB bus, and the program can be programmed and debugged using keil software on the PC side, and finally the number plate recognition result is displayed on the LCD. The recognition speed of the number plate recognition system reaches 0.4 seconds per picture, and the average correct rate reaches more than 98.5%, achieving the overall performance goal of the system. © 2020 ieee.

关键词： Field programmable gate arrays (FPGA)

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DSP implementation of a naturally commutated matrix converter open loop control

DSP implementation of a naturally commutated matrix converte...

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ieee International Symposium on Industrial Electronics

作者： Miliani, EH Depernet, D Kauffmann, JM UTBM L2ES Lab Rech Elect Electrotech & Syst F-90010 Belfort France

ISBN: (纸本)0780387384

This paper deals with the design concept of a naturally commutated matrix converter control system. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. Until few years ago, control of switch mode power supply systems used analog controllers. Digital signal Processors (DSP) are emerging as the processors of choice in monitoring and control of power electronics systems. In recent years, with the progress of high speed, lower cost digital signal processing (DSP) there has been a blossoming of the use of DSP techniques especially in power converters control. Using the 16-bit fixed point TMS320LF2407 DSP of Texas Instrument, a control strategy is implemented and tested on a 3 KW variable speed constant frequency generating system (VSCF) by using a naturally commutated matrix converter (NCMC).

关键词： Program processors

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FFT implementation TRADEOFFS.

FFT IMPLEMENTATION TRADEOFFS.

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Proceedings - ieee International Conference on Computer design: VLSI in Computers, ICCD '85.

作者： Tanaka, Michael I. TRW La Jolla CA USA TRW La Jolla CA USA

ISBN: (纸本)0818606428

Various methods for implementing radix-2 and radix-4 fast Fourier transform (FFT) algorithms are investigated. The hardware/speed tradeoffs of several system architectures are demonstrated. The FFT performance of a system depends not only on the number of multipliers and adders, but also on the number of require memory data reads and writes. In a well-designed system, the memory access requirements are well matched to the available arithmetic hardware.

关键词： signal processing

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design OF A PITCH SYNCHRONOUS INNOVATION CELP CODER FOR MOBILE COMMUNICATIONS

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ieee JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1995年第1期13卷 31-41页

作者： MANO, K MORIYA, T MIKI, S OHMURO, H IKEDA, K IKEDO, J NIPPON TELEGRAPH & TEL PUBL CORP YOKOSUKA ELECT COMMUN LABS RADIO COMMUN SYST LABS YOKOSUKA KANAGAWA 23803 JAPAN

This paper describes the design of a speech coder called pitch synchronous innovation CELP (PSI-CELP) for low bit-rate mobile communications. PSI-CELP is based on CELP, but has more adaptive excitation structures. In voiced frames, instead of conventional random excitation vectors, PSI-CELP converts even the random excitation vectors to have pitch periodicity by repeating stored random vectors as well as by using an adaptive codebook. In silent, unvoiced, and transient frames, the coder stops using the adaptive codebook and switches to fixed random codebooks. The PSI-CELP coder also implements novel structures and techniques: an FIR-type perceptual weighting filter using unquantized LPC parameters, a random codebook with a conjugate structure trained to be robust against channel errors, codebook search with delayed decision, a gain quantization with sloped amplitude, and a moving average prediction coding of LSP parameters. Our speech coder is implemented by DSP chips. Its coded speech quality at 3.6 kb/s with 2.0 kb/s redundancy is comparable to that of the Japanese full-rate VSELP coder at 6.7 kb/s with 4.5 kb/s redundancy. The basic structure of this PSI-CELP coder has been chosen as the Japanese half-rate speech codec for digital cellular telecommunications.

关键词： Technological innovation Speech Redundancy Mobile communication Switches Filters Linear predictive coding Robustness Delay Quantization

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Low-power embedded readout and processing system for ISFET sensors as measurement devices 9

Low-power embedded readout and processing system for ISFET s...

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9th ieee Latin American Symposium on Circuits and systems, LASCAS 2018

作者： Zorrilla, Luighi A. Viton Lezama, Jinmi Instituto Nacional de Investigación y Capacitación de Telecomunicaciones-INICTEL-UNI Universidad Nacional de Ingeniería Peru

ISBN: (纸本)9781538623114

Ion Sensitive Field Effect Transistors (ISFETs) have been widely used in different applications because of its rapid response and robustness. There are many structures of conditioning circuits proposed for ISFETs oriented to specific applications and a integrated solutions. This paper, proposes a completely embedded readout circuit and processing system to employ them as part of pH monitoring systems. The implementation was performed in the mixed signal microcontroller PSoC 5LP, with a classical constant-current and constant-voltage structure (CVCC) of 25μ and 300mV. Results shows a sensibility of 51mV/pH at 25°C and a compensated output with 0.02pH of tolerance and 0.02 of resolution. © 2018 ieee.

关键词： Timing circuits

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A linearization strategy for undersampling analog-to-digital converters

A linearization strategy for undersampling analog-to-digital...

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IMEKO TC4 International workshop on ADC Modelling, Testing and Data Converter Analysis and design 2011, IWADC 2011 and ieee 2011 ADC Forum

作者： Vallant, Georg Dederer, Jochen Epp, Michael Schlecker, Wolfgang Jondral, Friedrich K. Cassidian Electronics EADS Deutschland GmbH Woerthstrasse 85 D-89077 Ulm Germany Karlsruhe Institute of Technology Communications Engineering Lab. D-76128 Karlsruhe Germany

ISBN: (纸本)9781618392794

The ability of high performance Radar and Broadband systems to detect weak targets in presence of strong interferers or clutter is given by their Spurious Free Dynamic Range (SFDR). Although the signal-to-Noise-Ratio (SNR) necessary for detection may be improved by well-known system processing gains, the dynamic range is ultimately limited by distortion terms caused by nonlinear behaviour of receiver components. The Software Defined Radio (SDR) paradigm assigns the Analog-to-Digital Converter a key role in receiver design. For systems using IF- Subsampling, linearity requirements place a heavy burden on the ADC, as SFDR signifcantly degrades with increasing input frequency. As a consequence, the ADC can only be used at input frequencies fairly below its intrinsic full power bandwidth, restricting the systems IF placement. This contribution discusses the possibility of processing ADC output data in the digital domain to achieve improved linearity. The Volterra series approach of nonlinear systems and its constrained variants are discussed. We will show in detail that for higher input frequencies, dynamic errors cause the harmonic terms to loose their in-phase ability;in higher Nyquist zones a frequency-dependend dynamic phase error has to be considered. Assumptions are backed by an evaluation of coherent data from the LTC2208 (16 Bit, 120 MSPS). A specific correction algorithm incorporating the dynamic phase error will be presented, which yielded 25 dB SFDR improvement in the 7th Nyquist Zone (360-420 MHz). The reproducibility of correction results is considered in some detail.

关键词： signal to noise ratio

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