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Fine-grain asynchronous circuits for low-power high performance DSP implementations

Fine-grain asynchronous circuits for low-power high performa...

引用

ieee workshop on signal processing systems (SIPS)

作者： O. Garnica J. Lanchares R. Hermida Computer Archit. Department Universite Complutense de Madrid Madrid Spain

The aim of this paper is to present a new approach to creating low-power high-performance DSP using delay-insensitive asynchronous circuits. To attain this, we pipeline the asynchronous circuit at logic gate level in such a way that every functional unit can be pipelined in many stages, up to as many as half the number of gate levels. Also, we want to integrate this approach with the traditional method to synthesise synchronous circuits. In order to achieve this, we create a new library of gates which satisfy the constraints that asynchronous design requires. Finally, we present the results after building a pipelined multiplier with both synchronous and asynchronous approaches,.

关键词： Asynchronous circuits Digital signal processing Logic gates Delay Pipelines Circuit synthesis High level synthesis Logic circuits Libraries Pulse inverters

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design and implementation of "Medicine Chest Butler" Mobile App 5th

Design and Implementation of "Medicine Chest Butler" Mobile ...

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5th International Conference on Communications, signal processing, and systems (CSPS)

作者： Liu, Hengxin Chen, Jin Wang, Lujia Ji, Maolin Liu, Zeng Zhang, Hankun Tianjin Normal Univ Tianjin Key Lab Wireless Mobile Commun & Power Tr Tianjin 300387 Peoples R China

ISBN: (纸本)9789811032295;9789811032288

Most family does not implement intelligent management of the most commonly used medicine. Little research teams designed the family medicine chest intelligent management. This article is based on this background, committed to the development of smart phone App managing medicine and cloud management platform software system. The mobile terminal will also develop Android and Apple's dual-platform software. The medicine information is obtained by scanning the bar code. The backstage medicine information database maintenance and pharmaceutical science information releasing based on cloud-based platform architecture with more prominent security and scalability. The results show that the software can automatically remind medication and warn expired medicines. It can also well extend family health science knowledge.

关键词： Mobile app Family medicine management Health science

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design and implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture

Design and Implementation of JPEG 2000 Codec with Bit-Plane ...

引用

ieee workshop on signal processing systems (SIPS)

作者： Yu-Wei Chang Chih-Chi Chen Chun-Chia Chen Hung-Chi Fang Liang-Gee Chen DSP/IC Design Lab Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University Taipei Taiwan MediaTek Corporation Limited Hsinchu Taiwan

In this paper, an area-efficient JPEG 2000 codec is implemented on 6.1 mm 2 with 0.18 mum CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable of processing 78 MS/s for lossy coding at 1 bpp and 50 MS/s for lossless coding. Four techniques are used to implement this chip. The pre-compress ion rate-distortion optimization (pre-RDO) determines truncation points before coding to reduce computations for the EBC. The dataflow conversion and embedded compression reduces the tile memory bandwidth. The bit-plane parallel context formation enables scalable bit-plane coding. Experimental results show this chip has higher area efficiency than the previous works

关键词： Codecs Discrete wavelet transforms Bit rate Rate-distortion Throughput Tiles Transform coding Hardware Decoding CMOS technology

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implementation of Transparent Network Subsystem for PC Manageability

Implementation of Transparent Network Subsystem for PC Manag...

引用

1st International workshop on Cyber-Physical systems, Networks, and Applications (CPSNA) held during 17th ieee International Conference on Embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Nimura, Kazuaki Ito, Hidenobu Nakamura, Yousuke Guo, Zhaogong Yasaki, Kouich Miura, Takafumi Fujitsu Labs Ltd Nakahara Ku 1-1Kamikodanaka 4 Chome Kawasaki Kanagawa Japan Fujitsu Ltd Nakahara Ku Kawasaki Kanagawa Japan

ISBN: (纸本)9780769545028

By adding a subsystem that provides continuous network service to a host system such as a PC (Personal Computer), even while the host system is sleeping, it is possible to achieve efficient use of the system and energy reduction. Remote management is a typical example. Recently, to maintain network service anytime and anywhere, WWAN (Wireless Wide Area Network) technology such as 3G (3rd generation mobile telecommunications) has been employed. The design of the subsystem should be independent of the network device in terms of development cost because once modifications are made, they are dependent on a network device;this would lead to extra work being required to use the new network devices and retain the modification. Furthermore, modification to the logic or firmw are of a wireless network device may make re-certification necessary owing to rules and regulations for radio devices. Therefore, realization of a method that does not require any modification to wireless network devices, network drivers, and connection software is considered ideal;however, it has not been achieved thus far. In this paper, we propose a unique architecture for a subsystem that overcomes this design issue by introducing two elements to achieve host unaware network service: pseudo-response and bridge functionality for communicating through the subsystem. In general, a highly independent design contributes to processing overhead and tends to degrade performance. Hence, we prototype the subsystem on an ARM7 board and evaluate it using actual 3G network and cloud services. The results show that the proposed technique works transparently, even when the host system uses the network, and the required CPU (Central processing Unit) frequency is more than 70 MHz. Furthermore, it is confirmed that power reduction of around 60% can be achieved while downloading.

关键词： Device Network SUB-SYSTEM Host systems wireless WAN transparent network Personal computers Extra Work Firmware Energy conservation

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Unified inter-communication architecture for systems-on-chip

Unified inter-communication architecture for systems-on-chip

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18th ieee/IFIP International workshop on Rapid System Prototyping, RSP '07

作者： Rincón, F. Barba, J. Moya, F. Villanueva, F.J. Villa, D. Dondo, J. López, J.C. University of Castilla-La Mancha

ISBN: (纸本)0769528341

System-On-Chip (SoC) architectures are called to be the platform for an ever increasing number of interactive applications. One of the most time-consuming tasks is to define communication interfaces between the different components through a number of scattered heterogeneous processing nodes. That is not only a complex task, but also very specific to a certain implementation, which may limit the flexibility of the system, and makes the solutions difficult to reuse. In this paper, we describe how the distributed systems paradigm can be extended to provide a unified abstraction for both hardware and software components. Moreover, based on that abstraction, we define a low-overhead system-wide communication architecture that offers communication transparency between all kinds of components. Since the architecture is highly compatible with standard distributed object software systems, it also allows seamless interaction with any other kind of external network. © 2007 ieee.

关键词： Integrated circuits

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design and implementation of FPGA Based Reconfigurable Modulator for Satellite Applications

Design and Implementation of FPGA Based Reconfigurable Modul...

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ieee Region 10 Conference (TENCON)

作者： Bhandarkar, Kiran Goutham, T. Manikandan, J. Rao, V. Sambasiva PES Inst Technol Dept Elect & Commun Bangalore Karnataka India PES Univ Crucible Res & Innovat Bangalore Karnataka India PES Univ Ctr Res Space Sci & Technol Bangalore Karnataka India

ISBN: (纸本)9781509011346

Satellites have become the most predominant part of modern information transmission systems. They have played a pivotal role in development and advancement of technologies such as GPS Navigation, Disaster Management systems, Telemedicine services, Tele-education services, TV Broadcasting services etc. With advancements in these technologies there is a need for robust communication system that is capable of delivering stable and reliable data continually with constraints in hardware resources, communication bandwidth, transmission power and channel nonlinearity. To meet these requirements selection of precise modulation scheme is essential. This paper proposes the design and implementation of a reconfigurable modulator which is capable of performing modulation schemes that can effectively counter the limitations listed above. The proposed modulator can perform modulation schemes such as Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), Offset Quadrature Phase Shift Keying (OQPSK) and Unbalanced Quadrature Phase Shift Keying (UQPSK). Reconfiguration is an advanced technique for system design, wherein the same hardware resources can be reconfigured to provide different functionalities. The proposed modulator can dynamically reconfigure between modulation schemes as per the user requirement without any changes in the hardware. The proposed modulator is implemented on Virtex-5 FPGA. It is observed that 36.70 70.71 % of hardware resource and 70.253 % of power is saved by implementing the proposed reconfigurable modulator over conventional non-reconfigurable modulator.

关键词： Satellite Modulator Reconfigurable FPGA signal processing

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Buffer-On-Board Memory systems

Buffer-On-Board Memory Systems

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39th Annual International Symposium on Computer Architecture (ISCA)

作者： Cooper-Balis, Elliott Rosenfeld, Paul Jacob, Bruce Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)9781467304764

The design and implementation of the commodity memory architecture has resulted in significant performance and capacity limitations. To circumvent these limitations, designers and vendors have begun to place intermediate logic between the CPU and DRAM. This additional logic has two functions: to control the DRAM and to communicate with the CPU over a fast and narrow bus. The benefit provided by this logic is a reduction in pin-out to the memory system and increased signal integrity to the DRAM, allowing faster clock rates while maintaining capacity. While the few vendors utilizing this design have used the same general approach, their implementations vary greatly in their non-trivial details. A hardware-verified simulation suite is developed to accurately model and evaluate the behavior of this buffer-on-board memory system. A study of this design space is used to determine optimal use of the resources involved. This includes DRAM and bus organization, queue storage, and mapping schemes. Various constraints based on implementation costs are placed on simulated configurations to confirm that these optimizations apply to viable systems. Finally, full system simulations are performed to better understand how this memory system interacts with an operating system executing an application with the goal of uncovering behaviors not present in simple limit case simulations. When applying insights gleaned from these simulations, optimal performance can be achieved while still considering outside constraints (i.e., pin-out, power, and fabrication costs).

关键词： Cache Memory System DRAM1 gene central processing units Formal logic Vendors systems simulation signal integrity Operating systems simulating Motor buses

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design and implementation of On-chip Adaptive Router with Predictor for Regional Congestion

Design and Implementation of On-chip Adaptive Router with Pr...

引用

作者： Taniguchi, Masakazu Matsutani, Hiroki Yamasaki, Nobuyuki Keio Univ Dept Comp Sci Grad Sch Sci & Technol Yokohama Kanagawa Japan

ISBN: (纸本)9780769545028

Many-core processor is one of attractive solutions to Cyber-Physical systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2% compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6% and additional wiring requirement for each router port is only three.

关键词： Network-on-Chip adaptive routing modest hardware overhead prediction transmit congestion information

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An efficient linear-phase FIR filter architecture design for wireless embedded system

An efficient linear-phase FIR filter architecture design for...

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ieee workshop on signal processing systems (SIPS)

作者： Shyh Feng Lin Sheng-Chieh Huang Feng-Sung Yang Chung-Wei Ku Liang-Gee Chen DSP IC Design Lab Department of Electrical Engineering and Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan

This paper presents a novel approach for implementing power-efficient finite impulse response (FIR) filters that require less power consumption than traditional FIR filter implementations in wireless embedded systems. The proposed schemes impose to the direct form and achieve a certain reduction in the power consumption. A novel retimed structure and balanced modularized techniques are introduced and used to reduce the critical path to achieve hardware efficiency. A novel separated signed processing data flow scheme with modifying CSD (canonical signed digit) representation is also introduced and used to reduce the transition, which is the main source of power consumption. The combination of the proposed methods gives up to 71% reduction in power consumption with a slight area overhead.

关键词： Finite impulse response filter Embedded system Energy consumption Adders Pipeline processing Digital signal processing design engineering Power engineering and energy Hardware Noise reduction

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Infrastructure for numeric precision control in the Ptolemy environment

Infrastructure for numeric precision control in the Ptolemy ...

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Proceedings of the 1997 40th Midwest Symposium on Circuits and systems. Part 1 (of 2)

作者： Kim, Seehyun Lee, Edward A. Univ of California Berkeley United States

An abstract algorithm specification with idealized arithmetic must be made concrete with realistic arithmetic in the final phase of the `algorithm-to-implementation' design process in order to assess power consumption, hardware cost, and execution speed. In this paper, an infrastructure for refining an idealized model to get an architecture-dependent specification with finite precision is introduced. This infrastructure is built on top of the Ptolemy environment.

关键词： Digital signal processing

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