System-On-Chip (SoC) architectures are called to be the platform for an ever increasing number of interactive applications. One of the most time-consuming tasks is to define communication interfaces between the differ...
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As implementation technology has evolved into increasingly complex integrated circuits and time-to-market pressure incFeases day by day, system level design issues become more critical in the context of system on Chip...
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ISBN:
(纸本)0780395840
As implementation technology has evolved into increasingly complex integrated circuits and time-to-market pressure incFeases day by day, system level design issues become more critical in the context of system on Chip, which gives rise to the need for abstract executable. specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench specification and monitoring, facilitate this SoC modeling. In this paper, we present a transaction level modeling and verification method of ieee 802.15.3 MAC chip based on SystemC 2.0, which include an accuracy video model and a transaction level system model of ieee 802.15.3 MAC protocol. 'With the proposed scheme, *** get a reusable test bench which can be used at'both transaction level and register transfer level. In this case, the verification efficiency and accuracy will be greatly- improved. Specially, the transaction level model can significantly reduce product development risk while avoiding expensive over-engineering by ensuring the architecture meets all performance, power and cost requirements prior to implementation, allowing design resources to focus on Value-added functions.
This article describes a design and implementation of Current Harmonic Filter (CHF) to achieve quality of power. The CHF system encompasses the DC-AC power converter, dc-link capacitor, interface inductor and Digital ...
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Over the past years, there has been a considerable amount of research in the field of QoS support for (distributed) multimedia systems, ie, multimedia processing in, for example, a (networked) workstation environment....
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Over the past years, there has been a considerable amount of research in the field of QoS support for (distributed) multimedia systems, ie, multimedia processing in, for example, a (networked) workstation environment. QoS for multimedia systems is about media processing in software, using dynamically scalable functions, and trading resources for quality. Unlike QoS for mainstream multimedia systems, QoS support for high volume electronics (HVE) consumer terminals (CT), such as digital TV sets, digitally improved analog TV sets and STB (set-top boxes), has received little attention in the literature. This paper considers multimedia QoS for consumer terminals, with focus on the high-quality video domain.
Large-scale parallel implementation of matrix multiply and accumulate (MAC) core poses significant energy and area constraints in analog voltage domain under reduced supply voltage. A spatial multi-bit sub-1-V time-do...
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Large-scale parallel implementation of matrix multiply and accumulate (MAC) core poses significant energy and area constraints in analog voltage domain under reduced supply voltage. A spatial multi-bit sub-1-V time-domain matrix multiplier interface is presented using multi-hit hack-gate-driven delay elements as a scalable alternative for various approximate computing applications. A single-chip solution is demonstrated for two application modes: a high-throughput digitally driven mode for acceleration and a low-energy analog front-end mode for sensing. In accelerate mode, the system achieves an aggregate throughput of 21.6 GMAC/s with 9 TOPS/W energy efficiency. In sense mode, the system exhibits an energy efficiency of 55.3 TOPS/W for classification purpose. The proposed architecture utilizes 16-parallel 6-bit input vectors to perform matrix MAC computations using time-domain signalprocessing with 3-bit resistive weights at a suh-1-V supply of 0.7 V. An integrated speculative time-to-digital converter (is employed for 6-bit time-domain quantization with an on-chip mismatch calibration scheme. The prototype is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm(2). The system performs image recognition of handwritten digits using a machine learning scheme and demonstrates an average classification accuracy of 843% on the MNIST dataset. The resultant energy per MAC computation in the proposed spatial architecture is about 15x lower than a digital CMOS combinational logic-based parallel-tree MAC.
In the last decade demand for brightness in synchrotron light sources and luminosity in circular colliders led to construction of multiple high current storage rings. Many of these new machines require feedback system...
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ISBN:
(纸本)0780377389
In the last decade demand for brightness in synchrotron light sources and luminosity in circular colliders led to construction of multiple high current storage rings. Many of these new machines require feedback systems to achieve design stored beam currents. In the same time frame the rapid advances in the technology of digital signalprocessing allowed the implementation of these complex feedback systems. In this paper I concentrate on three applications of feedback to storage rings: orbit control in light sources, coupled-bunch instability control, and low-level RF control. Each of these applications is challenging in areas of processing bandwidth, algorithm complexity, and control of time-varying beam and system dynamics. I will review existing implementations as well as comment on promising future directions.
During the process of imagery, the factors including the motion between earth and the platform, atmosphere disturbance, out of focus, non-ideal sampling and so on, all can make the images blurred and degraded. Super r...
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design of a high-speed arithmetic unit with trigonometric computation has gained significant importance today. CORDIC is one such iterative algorithm that computes various trigonometric, logarithmic and transcendental...
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design of a high-speed arithmetic unit with trigonometric computation has gained significant importance today. CORDIC is one such iterative algorithm that computes various trigonometric, logarithmic and transcendental functions fast with high degree of accuracy. This paper proposes a new technique to compute these values with significant reduction in the number of iterations and power savings. The conventional CORDIC technique is achieved by rotating a vector in both counter-clockwise and clockwise directions. The proposed technique uses unidirectional rotation of the vector thereby reducing the complexity of the circuit and also the number of iterations. Tests were conducted to compute the sine and cosine values using both the conventional and the proposed approach and the results show almost insignificant error (similar to 10(-8)). This algorithm can be further used dominantly in any, signalprocessing applications. An analytical treatment on the algorithm and the architecture is given in this paper.
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signalprocessingsystems, which depend on the execution of large numbers of multiplications. Previously reported algori...
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The performance of multiplication is crucial for multimedia applications such as 3D graphics and signalprocessingsystems, which depend on the execution of large numbers of multiplications. Previously reported algorithms mainly focused on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Rather than focusing on reducing the partial products rows down to final sums and carries, our approach strives to generate fewer partial products rows. In turn, this influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. In addition to the speed improvement, our algorithm results in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation. The synthesis results of our multiplication algorithm using the Artisan TSMC 0.13um 1.2-Volt standard-cell library show 13 percent improvement in speed and 14 percent improvement in power savings for 8-bit x 8-bit multiplications (10 percent and 3 percent, respectively, for 16-bit x 16-bit multiplications) when compared to conventional multiplication algorithms.
Dataflow graph transformations are important in many contexts of SoC implementation, particularly in the domain of signalprocessing. Most previous work on dataflow graph transformations has focused on synchronous dat...
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