This paper describes a DSP implementation of probabilistic sound source localization algorithm. Time Delay of Arrival (TDOA) between two microphones through cross-correlation method has been used for sound localizatio...
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ISBN:
(纸本)9781424429233
This paper describes a DSP implementation of probabilistic sound source localization algorithm. Time Delay of Arrival (TDOA) between two microphones through cross-correlation method has been used for sound localization in our robot platforms. However, since cross-correlation values are highly dependent on the upcoming sound signal and acoustic environment, time delay values and localization results are easily perturbed. Here, probabilistic method for sound source localization is presented. And its DSP implementation is applied to the pan-tilt robot that we developed.
Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwidth, and hence naive hardware implemen...
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ISBN:
(纸本)9781424429233
Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwidth, and hence naive hardware implementation is prohibitive. In this paper, we first analyze the memory and bandwidth requirements of the technique from the hardware perspective. Then, we propose a tile-based belief propagation algorithm that works with existing data reuse schemes and achieves bandwidth reduction by a factor of 10 to 400. We apply the proposed algorithm to stereo estimation and show that its performance is comparable to the original algorithm.
In this paper, an efficient low-complexity robust adaptive beamforming method based on worst-case performance optimization is proposed. Lagrangian method was applied to obtain the expression for the robust adaptive we...
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ISBN:
(纸本)9781424422401
In this paper, an efficient low-complexity robust adaptive beamforming method based on worst-case performance optimization is proposed. Lagrangian method was applied to obtain the expression for the robust adaptive weight vector, which is optimized on the boundary of the steering vector uncertainty region, that is to say, in the worst mismatch case. Combining the constraint condition and the eigendecomposition of the array covariance matrix, root-finding method is used to obtain the optimal Lagrange multiplier. Then, the diagonal loading-like robust weight vector is achieved. ne implementation efficiency is greatly improved since the main computational burden is the eigendecomposition operator. Numerical results show that the performance of the proposed method is nearly identical to the robust Capon beamforming.
This paper presents the idea of sequential model-robust design of Experiments (DOE) for the identification of dynamic systems modeled with an Ordinary Differential Equation (ODE). The Studied DOE problem consists in s...
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ISBN:
(纸本)9781424423750
This paper presents the idea of sequential model-robust design of Experiments (DOE) for the identification of dynamic systems modeled with an Ordinary Differential Equation (ODE). The Studied DOE problem consists in selecting sequentially the instants where the measures will be done in order to best estimate the system's parameter. The robustness is achieved by considering a statistical representation of the model error defined as the difference between the true ODE and the ODE used in the model. The idea of modeling the model error with a statistical representation has been widely explored in the DOE literature for the identification of static systems. However, there have been little previous works that apply this idea for the identification of dynamic systems. This paper initiates an exploration of this idea in the context of first-order ODE. The model error is modeled by using a kernel-based representation (Gaussian process). A new criterion for the instant selection is constructed and tested on an illustrative example. The design reached with the proposed sequential robust criterion is compared with the design reached with the non-robust version of criterion and with the classical uniform design.
When combined with advanced FEC techniques such as the Turbo code and LDPC code, soft-output MIMO sphere decoders significantly outperform hard-output sphere decoders. Hence, algorithms and implementations of soft-out...
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ISBN:
(纸本)9781424429233
When combined with advanced FEC techniques such as the Turbo code and LDPC code, soft-output MIMO sphere decoders significantly outperform hard-output sphere decoders. Hence, algorithms and implementations of soft-output sphere decoders have attracted intensive interest in recent years. Practical soft-output sphere decoder implementations often consist of a list generator and a LLR generator. Most existing implementations focus on the list generator, and the LLR generator is implemented in a relatively straightforward way. However, the LLR generator accounts for a great part of the complexity. Our contribution is an implementation friendly low complexity multiplierless LLR generator. We apply selective and incremental updating, algebraic simplifications and strength reductions to reduce the algorithmic complexity and to eliminate all multiplications. When integrated with the SSFE list generator, our scheme not only remove 100% multiplications, but also remove 26% to 83% additions, 76% to 94% bit-shifts and 63% to 91% memory operations. Besides the algorithmic aspects, we extract the key data-flow block with well-defined control signals. This can be easily mapped onto micro-architectures and implemented as the data-path in ASICs, or a function unit in ASIPs.
One of the major and common requirements for all active microware sensors is generation of the transmit modulation signal-like chirp/LFM signal, MSK, etc., which can be generated by analog or digital means. With the i...
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One of the major and common requirements for all active microware sensors is generation of the transmit modulation signal-like chirp/LFM signal, MSK, etc., which can be generated by analog or digital means. With the increasing demands of side bandwidth, longer duration chirp signals in radar systems, digital signal generation, and processing has emerged as a preferred alternative. design and development of programmable and generic Digital Waveform Generator (DWG) system based on Xilinx Virtex XCV600 FPGA and high-speed DAC is carried out at the Space Applications Center. ISRO is to generate required transmit chirp signal of high time-bandwidth product (similar to 1000) for ISO's microwave radar sensor missions. This gives a detailed description of the design requirements, implementation details, salient performance features, and test results of this programmable and generic Digital Waveform Generator (DWG).
Modem microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power performance in every generation. To utili...
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ISBN:
(纸本)9781424429233
Modem microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power performance in every generation. To utilize the potential of such a system, signalprocessing algorithms have to be efficiently parallelized so that the load can be distributed evenly among the multiple processing units. In this paper, we study several advanced deterministic and stochastic signalprocessing algorithms and their computation using multiple processing units. Specifically, we consider two commonly used time-frequency signal representations, the short-time Fourier transform and the Wigner distribution, and we demonstrate their parallelization with low communication overhead. We also consider sequential Monte Carlo estimation techniques such as particle filtering, and we demonstrate that its multiple processor implementation requires large data exchanges and thus a high communication overhead. We propose a modified mapping scheme that reduces this overhead at the expense of a slight loss in accuracy, and we evaluate the performance of the scheme for a state estimation problem with respect to accuracy and scalability.
The application of Independent Component Analysis (ICA) algorithm can achieve a real time Blind signal Separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the l...
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ISBN:
(纸本)9781424423750
The application of Independent Component Analysis (ICA) algorithm can achieve a real time Blind signal Separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the limited size and of the microelectronics technology of the used hardware devices, many practical problem can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples. Hence, the system performance was degraded since we required the consumption of an important number of memory circuits with faster hardware execution time. Therefore, in order to improve the hardware performances of the device, in this paper, the authors proposed the sequential processing of one neuron hardware model based on Field Programmable Gate Array (FPCA) implementation. Such approach overcomes the interconnections complexities of the FPGA architecture Thus an optimal digital circuit design can be proposed to avoid the consumption of much hardware resources in which a maximum number of samples can be handled while maintaining high speed of hardware processing time. The proposed approach was demonstrated through the experimental study of TIMIT data base exhibiting a hardware execution time of 3.3 mu s to process 10000 samples with 57 Khz of sample rates to separate two output independent signals from two input mixed signals.
Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decima...
ISBN:
(纸本)9781424426577
Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to improve calculations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Also, the results with regard to delay obtained by means of an FPGA implementation of the method are shown.
This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When Implementing the FFT ...
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This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When Implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed In depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signalprocessingsystems on FPGA platforms.
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