The demand of processing speed in modern digital signalprocessing is huge and requires more computational power than a single processor can provide. To address these demands, distributed and parallel processing in em...
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ISBN:
(纸本)9780769533483
The demand of processing speed in modern digital signalprocessing is huge and requires more computational power than a single processor can provide. To address these demands, distributed and parallel processing in embedded systems is becoming a requirement. So it is essential to do research on algorithm and the parallel programming in the parallel embedded system. MPI (Message Passing Interface) is one of the most important parallel programming standards. Porting MPI to the embedded system will enhance application portability and make parallel programming much easier. This paper presents a novel design and implementation of MPI based on link DMA for DSP-based systems. Through computation the value of pi and PingPong, the results show that the implementation is suitable for parallel programming, especially suitable for large volume of data.
In this work the influence of the content of algorithms for primary processing of visual data on methods of their hardware and software implementation is studied. A formal method for construction architectures of visi...
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ISBN:
(纸本)9783000249891
In this work the influence of the content of algorithms for primary processing of visual data on methods of their hardware and software implementation is studied. A formal method for construction architectures of vision systems for solution of different scene recognition problems which are cost-optimal for given performance is presented. Digital signal processors (DSPs) and field programmable gate arrays (FPGAs) are Considered as the element base for construction of vision systems.
To design the hardware for image signalprocessing pipelines in digital still cameras (DSCs) and video camcoders, it is a dilemma for conventional solutions, such as application-specific integrated circuits (ASICs) an...
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To design the hardware for image signalprocessing pipelines in digital still cameras (DSCs) and video camcoders, it is a dilemma for conventional solutions, such as application-specific integrated circuits (ASICs) and digital signal processors (DSPs), to achieve high processing capability at low cost while maintaining high flexibility for various algorithms. With the observation of the characteristics of image signal-processing pipelines, including the different requirements for different operation modes and the algorithmic similarity of image-processing tasks, a new coarse-grained reconfigurable image stream processor (CRISP) is proposed in this paper. The design idea is to devote low-cost hardware for the requirements in the preview mode and add some hardware resources for higher flexibility and processing capability in the picture-taking mode. With the coarse-grained reconfigurable stage processing elements designed for image signal-processing tasks and the reconfigurable interconnection unit with unified communication protocol, CRISP can be reconfigured as an efficient dedicated hardware in the preview mode, and it can act like a flexible DSP for the picture-taking mode with different contexts. implementation result shows that the core (die) size is 5 mm(2) (7.72 mm(2)) with TSMC 0.18-mu m process, and the power consumption is 218 mW at 1.8 V. At the working frequency of 115 MHz, the processor is capable of processing 11 M-pixel still images at 10 fps for DSCs or 1920 x 1080 video frames at 55 fps for camcorders. CRISP can execute image pipelines 83 times faster than the state-of-the-art DSP with only about one-tenth die size.
A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate ...
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A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mu m CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm(2) of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm(2) of die area and 0.02 mW of power per tap.
This presents our design and development of an 8-channel adaptive beamforming antenna for new developments in radio technology: the emergence of chip-based components implementing the recently completed ieee 802.16d-2...
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This presents our design and development of an 8-channel adaptive beamforming antenna for new developments in radio technology: the emergence of chip-based components implementing the recently completed ieee 802.16d-2004 (WiMAX) radio standard [1-4]. WiMAX offers the potential of long-range (up to 50 miles) and high bandwidth (up to 50 Mb/s) radio links. Although the new WiMAX standard offers the potential for using smart, adaptive antennas, this functionality has not been implemented. Our design will serve as a common platform for testing adaptive array algorithms including direction of arrival (DOA) estimation, beamforming, and adaptive tracking, as well as complete wireless communication with a WiMAX Radio. Heavy emphasis will be placed on ease of implementation in a multi-channel / multi-user environment. In the future, we hope to expand this interface to support dynamic radio channel selection via direct interaction with radio hardware or implementation of a cognitive radio system(1,2).
Fuzzy controllers are used in many applications because of their rapid design by translating heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, they require parallel ...
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Fuzzy controllers are used in many applications because of their rapid design by translating heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, they require parallel processing and special operators (such as fuzzification or defuzzification) which are not available in standard digital signal processors (DSPs), thus complicating their direct implementation. This paper describes an efficient design methodology that allows starting with any kind of fuzzy controller and subsequently transforming it until a system suitable for easy DSP implementation is obtained. Such methodology is greatly aided by the design environment Xfuzzy 3. The parking problem of an autonomous robot is described to illustrate the steps of this methodology. Real experiments with the autonomous robot ROMEO 4R demonstrate efficiency of the designed fuzzy controller embedded into a stand-alone card based on a fixed-point DSP from Texas Instruments.
In this paper, we consider a receiver setup with fewer analog to digital convertors (ADC's) than antennas. An analog preprocessing network (APN) is placed before the ADC's to reduce power consumption in the re...
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ISBN:
(纸本)9781424420452
In this paper, we consider a receiver setup with fewer analog to digital convertors (ADC's) than antennas. An analog preprocessing network (APN) is placed before the ADC's to reduce power consumption in the receiver. A set of low resolution beamformers is used to design the APN and cancel contributions of interfering users. Simulation results show that introduction of such APN design algorithms for a narrowband channel with 3 to 4 interfering users, 6 antennas and 3 ADCs results in a reduction of the total consumed receiver power by 15%.
In modern digital signalprocessing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a fa...
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In modern digital signalprocessing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a faster barrel shifter block, which can be useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: i) timing-driven selection of multiple stages for merging, and ii) the design of the merged stage. In our proposed method, we define the notion of dual merged stage, where two stages are merged and the triple merged stage, where three stages are merged into a single composite stage. These merged stages are identified by using a timing-driven algorithm and are used in conjunction with some single stages of the traditional barrel shifter. The use of these merged stages helps reduce the depth of the proposed barrel shifter architecture, thereby improving the delay. The timing-driven nature of our algorithm helps produce a faster implementation for the overall shifter block. We have evaluated the performance of our design by using a number of technology libraries, timing constraints and shifter bit-widths. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (10.19% on average) than the shifter block generated by a commercially available datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.
Three phase rectifiers with switching frequencies of 500 kHz or more require high speed current controllers. At such high switching frequencies analog controllers as well as high speed DSP-systems have limited perform...
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ISBN:
(纸本)9781424425501
Three phase rectifiers with switching frequencies of 500 kHz or more require high speed current controllers. At such high switching frequencies analog controllers as well as high speed DSP-systems have limited performance. In this paper, two high speed current controller implementations using two different FPGAs - one for switching frequencies up to 1 MHz and one for switching frequencies beyond I MHz - are presented to overcome this performance limitation. Starting with the digital system design all the blocks of the signal chain, containing AID interface, digital controller implementation using HW-multipliers and implementation of a novel high speed, high resolution PWM are discussed and compared. Final measurements verify the performance of the controllers.
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