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ieee workshop on signal processing systems (SIPS)

作者： M. Elnamaky M. Ahmed-Ouameur D. Massicotte Laboratory of Signal and System Integration Department of Electrical and Computer Engineering Université du Québec à Trois Rivières Trois-rivieres QUE Canada

The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of the proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known maximum likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.

关键词： Field programmable gate arrays Channel estimation Least squares approximation Multiaccess communication Delay estimation Base stations Smoothing methods Filters Hardware Maximum likelihood detection

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Recognition of channel logo from analog video: An embedded realization

Recognition of channel logo from analog video: An embedded r...

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ieee International Symposium on Consumer Electronics

作者： Chattopadhyay, T. Sengupta, Soumik Sinha, Aniruddha Innovation Lab. Tata Consultancy Services Kolkata India

ISBN: (纸本)9781612848433

This paper presents the hardware implementation of the algorithm for recognizing the channel logos from the analog videos in real time in a commercially available DSP platform. This solution can be used for different value added services for connected TV like providing EPG on real time, real time TV viewership analysis, user view time analysis. This paper mainly focuses on the issues in optimization of dual core embedded realization of the algorithm that is performing efficiently in an x86 platform [1]. The optimization techniques we have used can save up to 150% of CPU cycles and also the proposed ARM DSP communication made the system an efficient one. © 2011 ieee.

关键词： ARM DSP communication Algorithm design and analysis Complexity theory Correlation DSP platform Digital signal processing Hardware Optimization TV TV viewership analysis analog video channel logo recognition digital signal processing chips digital television dual core embedded realization optimisation techniques embedded systems image recognition microprocessor chips optimisation user view time analysis value added services video signal processing

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Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition

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ieee TRANSACTIONS ON COMPUTERS 2015年第6期64卷 1579-1593页

作者： Ghandali, Samaneh Alizadeh, Bijan Fujita, Masahiro Navabi, Zainalabedin Univ Tehran Dept Elect & Comp Engn Tehran 14399515 Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Univ Tokyo VLSI Design & Educ Ctr VDEC Tokyo Japan

This paper concentrates on high-level data-flow optimization and synthesis techniques for datapath intensive designs such as those in Digital signal processing (DSP), computer graphics and embedded systems applications, which are modeled as polynomial computations over Z(2n1) x Z(2n2) x ... x Z(2nd) to Z(2m). Our main contribution in this paper is proposing an optimization method based on functional decomposition of multivariate polynomial in the form of f(x) = g(x) o h(x) + f(0) = g(h(x)) + f(0) to obtain good building blocks, and vanishing polynomials over Z(2m) to add/delete redundancy to/from given polynomial functions to extract further common sub-expressions. Experimental results for combinational implementation of the designs have shown an average saving of 38.85 and 18.85 percent in the number of gates and critical path delay, respectively, compared with the state-of-the-art techniques. Regarding the comparison with our previous works, the area and delay are improved by 10.87 and 11.22 percent, respectively. Furthermore, experimental results of sequential implementations have shown an average saving of 39.26 and 34.70 percent in the area and the latency, respectively, compared with the state-of-the-art techniques.

关键词： High-level synthesis polynomial datapath functional decomposition modulo optimization vanishing polynomial

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System level HW/SW partitioning and optimization tool

System level HW/SW partitioning and optimization tool

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Proceedings of the 1996 European design Automation Conference with EURO-VHDL'96 and Exhibition

作者： Schwiegershausen, M. Kropp, H. Pirsch, P. Univ of Hannover Hannover Germany

This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.

关键词： Multiprocessing systems

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DSP implemented dual 9600/7200 bps TCM modem for mobile communications over FM voice radios

DSP implemented dual 9600/7200 bps TCM modem for mobile comm...

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Proceedings of the 1997 6th ieee Pacific Rim Conference on Communications, Computers and signal processing. Part 1 (of 2)

作者： Mueller, A.Joseph Fung, Dominic Digital Dispatch Systems Inc Canada

This paper describes a dual 9600/7200 bit per second (bps) modem designed by the authors and implemented on a DSP based hardware platform. designed for use in mobile fading environments using inexpensive FM voice grade radios, the modem employs both 16 state, 16-QAM TCM (trellis coded modulation) and 16-state, 8-PSK TCM for a net data throughput of 7200 bps and 4800 bps, respectively (less some overhead for the radio attack time, synchronization and the multiple access contention protocol). The dual modem design implements a form of adaptive error control where the lower data rate 8-PSK TCM modem provides coverage where the 16-QAM TCM modem cannot. In addition to a description of the modem design and the challenges faced, this paper provides some insight into several of the key techniques used in the DSP implementation as well as theoretical and simulated bit error rate curves for the modem.

关键词： Modems

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Spatiotemporal Predictive Models for Irregularly Sampled Time Series 33

Spatiotemporal Predictive Models for Irregularly Sampled Tim...

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33rd ieee International workshop on Machine Learning for signal processing, MLSP 2023

作者： Le, Quang Chan, Francois D'Amours, Claude University of Ottawa Canada University of Ottawa Royal Military College of Canada Canada

ISBN: (纸本)9798350324112

To perform the long-term spatiotemporal sequence prediction (SSP) task with irregular time sampling assumptions, we build the sequence-to-sequence models based on the Trajectory Gated Recurrent Unit (TrajGRU) network and our proposed deep learning modules. First, we design a novel attention mechanism, namely Motion-based Attention (MA), and insert it into the TrajGRU network to create the TrajGRU-Attention model. In particular, the TrajGRU-Attention model can alleviate the impact of the vanishing gradient, which leads to the blurry effect in the long-term predictions and handle irregularly sampled time series. Second, leveraging the advances in Neural Ordinary Differential Equation (NODE) technique, we propose the TrajGRU-Attention-ODE model, which can be applied in continuous-time applications. To evaluate the performance of the proposed models, we select four available spatiotemporal datasets with increasing complexity levels, including the MovingMNIST, MovingMNIST++, KTH Action, and TAASRAD19. Our models outperform the state-of-the-art NODE model and generate better results than the standard TrajGRU model for SSP tasks with different types of time sampling. © 2023 ieee.

关键词： Continuous time systems

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design and evaluation of a collaborative online visualization and steering framework implementation for computational Grids 07

Design and evaluation of a collaborative online visualizatio...

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8th ieee/ACM International Conference on Grid Computing

作者： Riedel, Morris Eickermann, Thomas Frings, Wolfgang Dominiczak, Sonja Mallmann, Daniel Duessel, Thomas Streit, Achim Gibbon, Paul Wolf, Felix Schiffmann, Wolfram Lippert, Thomas Forschungszentrum Julich John Von Neumann Inst Comp Cent Inst Appl Math Postfach 1913 D-52425 Julich Germany Rhein Westfal TH Aachen Dept Comp Sci D-52056 Aachen Germany Univ Hagen Inst Comp Architecture Dept Comp Sci D-58097 Hagen Germany

ISBN: (纸本)9781424415595

Today's large-scale scientific research often relies on the collaborative use of a Grid or e-Science infrastructure (e.g. DEISA, EGEE, TeraGrid, OSG) with computational, storage, or other types of physical resources. One of the goals of these emerging infrastructures is to support the work of scientists with advanced problem-solving tools. Many e-Science applications within these infrastructures aim at simulations of a scientific problem on powerful parallel computing resources. Typically, a researcher first performs a simulation for some fixed amount of time and then analyses results in a separate post-processing step, for instance, by viewing results in visualizations. In earlier work we have described early prototypes of a Collaborative Online Visualization and Steering (COVS) Framework in Grids that performs both - simulation and visualization - at the same time (online) to increase the efficiency of e-Scientists. This paper evaluates the evolved mature reference implementation of the COVS framework design that is ready for production usage within Web service-based Grid and e-Science infrastructures.

关键词： Online Communities/Technical Collaboration Visualization Grid computing Collaborative work Computational modeling Large-scale systems Physics computing Problem-solving Parallel processing Analytical models

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Improved processing Circuit for MEMS Accelerometer as a Respiration Sensor 7

Improved Processing Circuit for MEMS Accelerometer as a Resp...

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7th International Conference on Advances in Biomedical Engineering, ICABME 2023

作者： Al-Zaben, Awad Al-Naami, Bassam Al-Omari, Ghadeer Yarmouk University Hijjawi Faculty for Engineering Technology Biomedical Systems and Medical Informatics Department Jordan Engineering College Hashemaite University Biomedical Engineering Department Jordan

ISBN: (纸本)9798350325850

Capturing respiration signal using a microelectromechanical (MEMS) accelerometer is a challenging task. The design of the interface circuit of the sensor must consider the characteristics of the respiration signal resulting from abdominal movement. It is mainly characterized by very low magnitude and low-frequency contents. Hence, any DC offset or drift in the sensor's response is a key design factor of the circuit. In addition, the OnChip processing circuit of the sensor itself may introduce DC offset and limit the lower range of the frequency response. This paper presents a design and implementation of a signal processing interface circuit that can be used to process MEMS accelerometer output to capture respiration signals. The circuit consists of a low pass filter that captures the DC component of the signal, then a differential amplifier that subtracts the estimated DC component from the signal followed by amplification. The circuit is self-calibrated by the position of the sensor. The circuit diagram, evaluation results, and validation of the circuit are presented in this paper. © 2023 ieee.

关键词： Accelerometers

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Flexible real time signal filtering in space using reconfigurable logic 14

Flexible real time signal filtering in space using reconfigu...

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14th International Conference on Digital signal processing, DSP 2002

作者： Dawood, Anwar S. Williams, John A. Visser, Stephen J. Cooperative Research Centre for Satellite Systems School of Electrical and Electronic Systems Engineering Queensland University of Technology GPO Box 2434 BrisbaneQLD4001 Australia

ISBN: (纸本)0780375033

The High Performance Computing (IIPC-I) payload is an innovative computing device designed for deployment on the Australian scientific mission satellite FedSat. HPC-l will validate and evaluate the practicality of using reconfigurable Field Programmable Gate Array (FPGA) technology in the space environment. The deployment of re- configurable FPGA technology on-board satellites is a very promising solution for digital signal processing in the challenging space environment, offering tremendous flexibility to adapt to changing operation Equirements, while achieving very high performance. Such combined flexibility and performance is not found in conventional signal processing architectures. This paper presents the design and implementation on HPC-I of two common digital signal filtering algorithms, a 4-tap low pass FIR filter and a 32-tap moving average filter. The flexibility and adaptability of the system is discussed in the context of more complex functionality and changing operation requirements. © 2002 ieee.

关键词： Taps

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design of High-Speed Receiver Based on Parallel processing 6

Design of High-Speed Receiver Based on Parallel Processing

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6th International Conference on Information Communication and signal processing, ICICSP 2023

作者： Yang, Yizhou Gu, Peng Zhou, Shanyu Liu, Guangzu School of Electronic Engineering and Optical Engineering Nanjing University of Science and Technology Jiangsu Nanjing China

ISBN: (纸本)9798350339994

In recent years, with the development of information technology, the demand for information transmission rates in various fields has increased from hundreds of Mbps to several Gbps, and even tens of Gbps. Studies have shown that the required wireless transmission rates in the next decade will reach 5-15 Gbps. However, current communication systems are unable to provide sufficiently high data transfer rates to meet the growing demand for high-speed data transmission. Therefore, this paper primarily focuses on the research of full-parallel demodulation techniques and their hardware implementation for high-rate modulation signals, aiming to break through key technologies such as the design of full-parallel demodulation architecture, parallel timing synchronization, and parallel carrier synchronization in high-speed demodulation. © 2023 ieee.

关键词： APRX carrier synchronization frequency-domain parallel demodulation architecture timing synchronization

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