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ieee Micro

作者： ieee Computer Society.

出版社：IEEE COMPUTER SOC

ieee Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems. The articles in this journal are peer reviewed in accordance with the requirements set forth in the ieee PSPB Operations Manual (sections 8.2.1.C & 8.2.2.A). Each published article was reviewed by a minimum of two independent reviewers using a single-blind peer review process, where the identities of the reviewers are not known to the authors, but the reviewers know the identities of the authors. Articles will be screened for plagiarism before acceptance.

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Efficient Hardware implementation of Multi-Armed Bandit Algorithms for RIS-Aided Wireless Networks

Efficient Hardware Implementation of Multi-Armed Bandit Algo...

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Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), ieee Conference on

作者： Ishaan Sharma Rohit Kumar Sumit J Darak Electronics and Communications Department Delhi Technological University India Electronics and Communications Department IIIT Delhi India

ISBN: (数字)9798331521691

ISBN: (纸本)9798331521707

The potential of Reconfigurable Intelligent Surfaces (RIS) to support next-generation wireless communication systems has recently garnered significant attention. This research ad-dresses the challenge of optimizing RIS-aided wireless networks, where RIS technology enhances signal control and coverage. However, in complex scenarios with multiple RIS units and receivers, selecting the optimal RIS blocks to maximize SNR becomes computationally intensive. Traditional methods relying on complete channel state information face high latency and scalability issues in dynamic environments. To overcome this, we propose a synthesizable Multi-Armed Bandit (MAB) algorithm, specifically the Upper Confidence Bound (UCB) algorithm, for RIS selection in real-time deployments on the PolarFire SoC. The focus is on efficient decision-making within constrained computational environments, leveraging a hardware-software co-design approach to optimize resource utilization. The implementation efficiently maps the algorithm to PolarFire SoC resources, including logic, memory, and I/O components, ensuring real-time processing performance in smart wireless environments.

关键词： Technological innovation Wireless networks Heuristic algorithms Scalability Receivers Reconfigurable intelligent surfaces Real-time systems Resource management Surface treatment signal to noise ratio

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A Mixed-signal ASIC for ISO 11784/5 Compliant Animal RFID Readers

A Mixed-Signal ASIC for ISO 11784/5 Compliant Animal RFID Re...

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ieee Latin American Symposium on Circuits and systems (LASCAS)

作者： Lucio Barbieri Matías Miguez Joel Gak Alfredo Arnaud Departamento de Ingeniería Universidad Católica del Uruguay Montevideo Uruguay

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

In this work the design and implementation of a fully integrated ISO 11784/5 RFID reader front-end ASIC is presented, for both HDX and FDX transponder types. The ASIC was designed in a 0.18 μm. CMOS-HV technology, and includes the two analog front-ends which are multiplexed to a single 10-bit, 8-bit ENOB ADC, and a digital signal processing unit. The digital block is integrated by a field-programmable, re-usable, set of IIR filters to further process the RFID signals, working @1.25MSPS and composed of ~ 20k logic gates (61% utilization ratio). The designed ASIC area (PADs not included) is 0.8mm 2 .

关键词： Multiplexing Protocols Animals ISO Standards IIR filters Logic gates Hardware Transponders Logic Radiofrequency identification

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Efficient Sampling Allocation Strategies for General Graph-Filter-Based signal Recovery

arXiv

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arXiv 2025年

作者： Dabush, Lital Routtenberg, Tirza School of Electrical and Computer Engineering Ben-Gurion University of the Negev Beer-Sheva84105 Israel

Sensor placement plays a crucial role in graph signal recovery in underdetermined systems. In this paper, we present the graph-filtered regularized maximum likelihood (GFR-ML) estimator of graph signals, which integrates general graph filtering with regularization to enhance signal recovery performance under a limited number of sensors. Then, we investigate task-based sampling allocation aimed at minimizing the mean squared error (MSE) of the GFR-ML estimator by wisely choosing sensor placement. Since this MSE depends on the unknown graph signals to be estimated, we propose four cost functions for the optimization of the sampling allocation: the biased Cramér-Rao bound (bCRB), the worst-case MSE (WC-MSE), the Bayesian MSE (BMSE), and the worst-case BMSE (WC-BMSE), where the last two assume a Gaussian prior. We investigate the properties of these cost functions and develop two algorithms for their practical implementation: 1) the straightforward greedy algorithm;and 2) the alternating projection gradient descent (PGD) algorithm that reduces the computational complexity. Simulation results on synthetic and real-world datasets of the ieee 118-bus power system and the Minnesota road network demonstrate that the proposed sampling allocation methods reduce the MSE by up to 50% compared to the common sampling methods A-design, E-design, and LR-design in the tested scenarios. Thus, the proposed methods improve the estimation performance and reduce the required number of measurements in graph signal processing (GSP)-based signal recovery in the case of underdetermined systems. Copyright © 2025, The Authors. All rights reserved.

关键词： Cramer-Rao bounds

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An FFT Accelerator IP Core Implemented on FPGA

An FFT Accelerator IP Core Implemented on FPGA

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ieee Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Vamsi Krishna Challagundla Jayaraj U Kidav Shashank Kumar Singh Anirban Jyoti Hati Sai Kumar Mandiga Dept. of ESE National Institute of Electronics and Information Technology (NIELIT) Aurangabad India Scientist G Dept. of ESE National Institute of Electronics and Information Technology (NIELIT) Aurangabad India Scientist B Dept. of ESE National Institute of Electronics and Information Technology (NIELIT) Aurangabad India Scientist C Dept. of ESE National Institute of Electronics and Information Technology (NIELIT) Aurangabad India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

The main objective of this project is to design and implement a Fast Fourier Transform (FFT) IP core. Due to its ability to provide accurate frequency domain analysis of time domain signals, the FFT technique is indispensable in many applications related to digital signal processing. The implementation is based on the radix-2 method, whose lower computational complexity and hardware resource efficiency make it a good fit for FPGA platforms. With its robust FPGA and ARM CortexA53 processors, the ZCU104 board provides an adaptable environment for creating unique IP cores and incorporating them into more complex *** objective of this project is to use the Zynq SoC’s hardware acceleration capabilities to improve the FFT core for speed and resource consumption. The ZCU104 board is used to test and validate the built IP core, proving its usefulness for real-time signal processing applications. As compared to software-based FFT implementations, the results demonstrate a notable boost in performance, underscoring the potential of FPGA based solutions in high performance computing jobs.

关键词： Program processors Fast Fourier transforms signal processing algorithms Throughput Real-time systems Radar signal processing IP networks Time-domain analysis signal analysis Field programmable gate arrays

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A Low-Complexity and High-Throughput Hardware design for Lempel-Ziv 4 Compression Algorithm

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ieee TRANSACTIONS ON CIRCUITS AND systems I-REGULAR PAPERS 2025年

作者： Chen, Tao Song, Suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The Lempel-Ziv (LZ) 4 compression algorithm, widely used in data transmission and storage, faces the challenge of high-speed implementation and increased complexity in the era of big data. Therefore, this paper proposes a single-core parallel architecture for LZ4 algorithm with high throughput and low complexity. Firstly, to enhance throughput, two innovative approaches are introduced from the perspective of parallelism and frequency with an acceptable compression ratio loss: each parallelization window is restricted to performing a single match, bridging the gap between actual and theoretical parallelism;the feedback loop in the circuit is broken by utilizing the spatial correlation between adjacent matches for higher frequency. Secondly, two optimization schemes are employed on resource-consuming modules to achieve low complexity. Multi-port hash tables using Live Value Table (LVT) are improved based on inherent data characteristics, significantly reducing the hardware resource consumption while ensuring excellent scalability on hash table depth and frequency. The match comparison operation is moved ahead, further reducing the logic resources by 64.36%. Finally, our design is implemented on FPGA and ASIC platforms. Experimental results on FPGA demonstrate that the proposed architecture achieves a throughput of 17.39 Gb/s, exhibiting a 2.86x improvement over the state-of-the-art, along with a 6.46x enhancement in area efficiency. Further optimizations including Canonic Signed Digit (CSD) coding and computational reuse on the ASIC platform result in a 45x improvement in area efficiency.

关键词： Hardware Throughput Parallel processing Complexity theory Field programmable gate arrays Compression algorithms Encoding signal processing algorithms Parallel architectures Logic Lossless data compression LZ4 algorithm FPGA ASIC high throughput low complexity hardware accelerator

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Fully Digital Ultra-low-bit Linear Embedding Beamforming System with Quantization Compensation

Fully Digital Ultra-low-bit Linear Embedding Beamforming Sys...

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ieee Radio and Wireless Symposium (RWS formerly RAWCON)

作者： Xiangyu Mao Coleman DeLude Wei-Chun Wang Justin Romberg Saibal Mukhopadhyay School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

ISBN: (数字)9798350377743

ISBN: (纸本)9798350377750

We propose the first digital ultra-low-bit precision implementation of a Linear Embedded Beamforming (LE-BF) system, which transforms high-dimensional input signals into low-dimensional outputs. The use of quantization compensation in this operation ensures beamforming performance is preserved. The system then processes the low-dimensional outputs to generate the final output with lower power consumption. The paper presents two different implementations of LE-BF systems: 1) An FPGA-based 2-bit LE-BF system configured with 64 inputs and 1 output, achieving a $12.4 \times$ decrease in design component utilization and a $11.2 \times$ decrease in power consumption compared to corresponding traditional True-Time-Delay digital beamforming (TTD-DBF) designs. 2) An ASIC-based (TSMC 28nm) 2-bit LE-BF configured with 256 inputs and 1 output, exhibiting a $18.7 \times$ greater efficiency in both design area and power consumption compared to corresponding TTDDBF designs. The ASIC-based system is capable of supporting a 1 GHz instantaneous bandwidth.

关键词： Wireless communication Quantization (signal) Power demand Accuracy Array signal processing Transforms Bandwidth Hardware

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design and implementation of IoT-Based Smart Fuel Monitoring System

Design and Implementation of IoT-Based Smart Fuel Monitoring...

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International Colloquium on signal processing & Its Applications, CSPA

作者： Islam Mohamedalfatih Ahmed Abdalmaged Safaa Najah Saud Al-Humairi Asmaa Mahfoudh Hezam Al-Hakimi Aparna Kumari School of Graduate Studies Management and Science University Shah Alam Selangor Malaysia Faculty of Information Sciences and Engineering Management and Science University Shah Alam Selangor Malaysia Department of Computer Science and Engineering Institute of Technology Nirma University Ahmedabad India

ISBN: (数字)9798331522193

ISBN: (纸本)9798331522209

The fast growth of the 'Internet of Things' (IoT) has impacted on several sectors, including fuel management. This paper describes the design, fabrication, and implementation of an IoT-based smart fuel monitoring system to improve the effectiveness of using fuel resources while minimizing losses and optimizing processes. A Rasp berry Pi controller with various sensors tracks essential parameters such as fuel level, temperature, pressure, pH, and gas levels. The system also provides for processing and presenting the collected data through a mobile application and a website, making it possible to manage the system further from the users via remote control. The system was tested using two fuel types, Benzene and Diesel, and it was effective in fuel parameters management. Results established that the pressure of Benzene was reasonably constant, and it was about 14.8 psi after reaching equilibrium. In contrast, the pressure returned to 14.7 psi value for Diesel, which was its initial value. The temperature readings were constant throughout the experiment, with the benzene temperature being higher than Diesel. The system also differentiated between pH levels, keeping Benzene at 6.9 while Diesel at around 7. These results prove the capabilities and efficiency of this system in anomaly detection, fuel adulteration, and fuel theft prevention, thus solving modern solutions in fuel management.

关键词： Temperature sensors Temperature measurement PI control Process control Real-time systems Temperature control Fuels Internet of Things Monitoring Intelligent sensors

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Indigenous design and Development of Interface Board for TMS320F28335 DSP and Programming via MATLAB Simulink Embedded Coder

Indigenous Design and Development of Interface Board for TMS...

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Smart and Sustainable Developments in Electrical Engineering (SSDEE), ieee International Conference on

作者： Urbesh Sarkar Prasun Mishra Smart Power Electronics & Electrical Drives Lab Advanced Technology Development Centre Indian Institute of Technology Kharagpur Kharagpur India

ISBN: (数字)9798331542108

ISBN: (纸本)9798331542115

This paper presents an indigenous design and development of an interface board, interfacing different micro-controller peripherals and sensors, for the Texas Instruments TMS320F28335 Digital signal Processor (DSP), with a focus on its integration with MATLAB Simulink Embedded Coder to do efficient programming and code deployment. The developed interface board, having essential hardware, provides a reliable and seamless connection between the TMS320F28335 DSP and the development environment, enabling real-time control, signal and data processing tasks for various embedded control systems. MATLAB Simulink Embedded Coder is employed to generate C code for the TMS320F28335 through automatic code generation and direct deployment of algorithms to the DSP streamlining the development process for embedded applications. This paper discusses the hardware components of the interface board along with communication protocols and configuration of various C2000 microcontroller blocks for software integration with MATLAB, highlighting its versatility and ease of use for real-time embedded system development. A case study of real-time implementation of closed-loop v/f control of induction motor is presented and the obtained results demonstrate the efficacy of the interface board while enabling its efficient programming and operation. This work contributes a viable, customizable solution for the students, researchers, and engineers started working with TMS320F28335 DSPs and Embedded Coder, promoting enhanced productivity and flexibility in embedded system development.

关键词： Motor drives Codes Induction motors Embedded systems Software packages Programming Real-time systems Hardware Sensors MATLAB

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Development and Evaluation of a Calibration Methodology for Pressure-Resistive Sensors in a Specialized Diagnostic Laboratory

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ieee Access 2025年 13卷 77642-77655页

作者： Roman Zelník Roman Ruzarovsky Tibor Horak Martin Csekei Dávid Michal Ján Šido Institute of Manufacturing Technologies Faculty of Materials Science and Technology in Trnava Slovak University of Technology in Bratislava Trnava Slovakia Institute of Applied Informatics Automation and Mechatronics Faculty of Materials Science and Technology in Trnava Slovak University of Technology in Bratislava Trnava Slovakia

This paper presents the development and evaluation of a calibration methodology for pressure-resistive sensors, implemented within a specialised diagnostic laboratory. The approach utilises algorithmic correction, structured measurement routines, and real-time signal processing to perform sensor calibration exclusively at the software level, without requiring hardware intervention. A custom sensor profiling framework has been designed to enable precise analysis of sensor characteristics, degradation, and long-term behaviour. The calibration algorithm employs mathematical interpolation and dataset synchronisation techniques to enhance accuracy and reduce measurement uncertainty. Experimental validation demonstrated a reduction in average deviation from 18.1% to 1.1%, with an overall tolerance range of just 2.6%. These results confirm the effectiveness of the proposed methodology in improving sensor precision and stability. The system is particularly suited for industrial environments where reliable pressure sensing is essential for safety, efficiency, and predictive maintenance.

关键词： Sensors Calibration Accuracy Reliability Pressure sensors Mechanical sensors Sensor phenomena and characterization Pressure measurement Sensor systems Temperature measurement

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