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Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator 33

Co-design of a novel CMOS highly parallel, low-power, multi-...

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33rd Microelectronics Design & Test Symposium (MDTS)

作者： Hokenmaier, W. Jurasek, R. Bowen, E. Granger, R. Odom, D. Green Mt Semicond Inc Semicond Hardware Dev Burlington VT 05401 USA Non Von LLC Software Algorithm & Architecture Design Lyme NH USA

ISBN: (纸本)9798350364651;9798350364668

Why do security cameras, sensors, and siri use cloud servers instead of on-board computation? The lack of very-lowpower, high-performance chips greatly limits the ability to field untethered edge devices. We present the NV-1, a new low-power ASIC AI processor that greatly accelerates parallel processing (similar to 10X) with dramatic reduction in energy consumption (> 100X), via many parallel combined processor-memory units, i.e., a drastically non-von-Neumann architecture, allowing very large numbers of independent processing streams without bottlenecks due to typical monolithic memory. The current initial prototype fab arises from a successful co-development effort between algorithm- and software-driven architectural design and VLSI design realities. An innovative communication protocol minimizes power usage, and data transport costs among nodes were vastly reduced by eliminating the address bus, through local target address matching. Throughout the development process, the software/architecture team was able to innovate alongside the circuit design team's implementation effort. A digital twin of the proposed hardware was developed early on to ensure that the technical implementation met the architectural specifications, and indeed the predicted performance metrics have now been thoroughly verified in real hardware test data. The resulting device is currently being used in a fielded edge sensor application;additional proofs of principle are in progress demonstrating the proof on the ground of this new real-world extremely low-power high-performance ASIC device.

关键词： co-design low-power design parallel processors neural network accelerator memory instruction set design

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Handwritten Digit Recognition using Convolution Neural Networks 12

Handwritten Digit Recognition using Convolution Neural Netwo...

引用

ieee 12th Annual Computing and communication workshop and Conference (CCWC)

作者： Rajput, Shailesh S. Choi, Yoonsuk Calif State Univ Fullerton Comp Engn Program Fullerton CA 92634 USA

ISBN: (纸本)9781665483032

Deep learning has witnessed a significant evolution recently with growth in high-performance devices and research in the neural network. The central aspect of this paper is to discuss the deep learning concept ideas and problems faced during training the model and come with a solution for better accuracy, illustrated by digit recognition and prediction using a convolution neural network. The first part of the research focused on the techniques used for training models in neural networks and enlightened the previous study in digit recognition. The second half of the paper detailed the concept of the proposed model for digit recognition with increased accuracy by preprocessing samples and ensemble of two or more models with different architectures and preprocessing. Preprocessing of samples and implementation of the model architecture is done using python.

关键词： ensemble models deep learning digit recognition model architecture

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Building a portable parallel asynchronous PDE solver using Kokkos

Building a portable parallel asynchronous PDE solver using K...

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ieee International Conference on high performance Computing workshops (HiPCW)

作者： Ranjan Bhat Konduri Aditya Department of Computer Science and Engineering Manipal Academy of Higher Education Manipal Institute of Technology Manipal India Department of Computational and Data Sciences Indian Institute of Science Bengaluru India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

In this study, we outline the design and implementation of a portable massively parallel asynchronous solver for time-dependent partial differential equations (PDEs). The solver is implemented using Kokkos library for portability across different node architectures and is coupled with the communication-avoiding algorithm that relaxes the communication across nodes, thus improving the scalability. Asynchrony-tolerant finite difference schemes for spatial derivatives along with the low storage Runge-Kutta scheme for time integration are used to achieve high-order accuracy. The efficacy of the implementation is demonstrated using a mini-app that solves the three-dimensional diffusion problem.

关键词： Scalability Partial differential equations high performance computing Conferences Buildings Computer architecture Benchmark testing Libraries performance analysis Finite difference methods

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EbAcraft: Engaging Local Communities in Learning About Ecosystem-Based Adaptation for Coastal Cities in Europe 19

EbAcraft: Engaging Local Communities in Learning About Ecosy...

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19th ieee International Conference on e-Science, e-Science 2023

作者： De Sena, Ítalo Cocco, Chiara Brůža, Vojtěch Lenicolais, Pierre Crowley, Saul Pilla, Francesco School of Architecture Planning and Environmental Policy University College Dublin Dublin Ireland Masaryk University Faculty of Informatics Brno Czech Republic Ecole Centrale de Marseille Marseille France

ISBN: (纸本)9798350322231

Coastal cities are confronted with the imperative to adapt to the impacts of climate change. Within the realm of adaptation strategies, ecosystem-based adaptation (EbA) has emerged as a prominent solution for enhancing the resilience of coastal communities. However, a significant obstacle lies in the effective dissemination and comprehension of these innovative climate adaptation strategies among local populations. communication serves as a pivotal factor in facilitating an understanding of the multifaceted challenges posed by climate change. The engagement of children in communication initiatives has proven to be effective when promoting adoption of these types of solutions, as they also support the engagement of other local societal groups, such as their families. Minecraft, a highly popular digital game, presents a compelling platform for the creation of public online servers featuring customisable mechanics. Leveraging this potential, our study introduces EbAcraft, a game specifically developed to engross and challenge players in the collaborative implementation of EbAs tailored for a fictional coastal city. By contextualising the climate change challenges, presenting potential solutions, and inviting participation within a virtual environment, EbAcraft was conceived as an engaging tool to foster comprehension and encourage active involvement. The game was launched during the EU Green Week 2023 as an online workshop, inviting participants from 10 different European cities as part of the SCORE Project and supporting multilingual accessibility with translations available in 11 languages. SCORE Coastal Cities Living Labs (CCLLs) promoted the event within their respective communities through schools and social media, resulting in the participation of 33 players over 7 hours of online event. © 2023 ieee.

关键词： Climate change

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Overlapping communication and Computation with ExaMPI's Strong Progress and Modern C plus plus Design

Overlapping Communication and Computation with ExaMPI's Stro...

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8th workshop on Exascale MPI (ExaMPI)

作者： Schafer, Derek Hines, Thomas Suggs, Evan Drake Rufenacht, Martin Skjellum, Anthony Univ Tennessee Chattanooga TN 37403 USA Leibniz Supercomp Ctr Bavaria Germany

ISBN: (纸本)9781665411080

ExaMPI is a modern, C++17+ MPI implementation designed for modularity, extensibility, and understandability. In this work, we overview functionality new to ExaMPI since its initial release, including Libfabric-based network transport support. We also explain our rationale for why and how we choose to add new MPI features (and defer others). Lastly, we measured the latency of the aforementioned transports in ExaMPI and found that ExaMPI, while having slightly higher latency than other production MPIs, is competitive. It is no longer uncommon to see MPI applications using extra MPI calls during non-blocking MPI operations to coax MPI's progress engine. Strong, asynchronous progress (aka application bypass) in MPI is instead based on the premise that an application asks MPI to perform a non-blocking communication in the background and MPI completes said communication without requiring any additional MPI calls from the application to advance the underlying transport. Strong progress often requires an additional background thread, but with the current trend in exascale computing, cores appear to be in excess. Indeed, for earlier MPI implementations that supported it well, strong progress enabled overlap and reduced time to completion for some MPI applications. However, enabling or adding strong progress to existing MPI implementations is not straightforward;changing such implementations is cumbersome, difficult, invasive, and time-consuming-a key motivation for our research MPI implementation, ExaMPI. Specifically, we tested the ability for ExaMPI's strong progress engine to enable overlap communication and computation, finding that considerable overlap is achieved without needing additional MPI "helper" calls such as MPI_Test.

关键词： MPI middleware architecture parallel programming models overlap performance portability

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A Comparative Study on performance Validation of Ring Oscillator for UWB & Low Power

A Comparative Study on Performance Validation of Ring Oscill...

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Conference on Information and communication Technology (CICT)

作者： Rahul Agarwal Manish Kumar GLA University Mathura India

ISBN: (数字)9781665473125

ISBN: (纸本)9781665473132

With the advancement of internet of things voltage controlled oscillator (VCO's) are most pivotal basic building blocks, where they are predominantly used as a high frequency clock generating subsystems, notably in cutting edge wireless systems used for sub 5G band or millimetre range of frequency that either encompasses the implementation of the VCO with high oscillation frequency and low close-in phase noise, in PLL and in frequency synthesizer. This paper compares the performance parameters of CMOS Ring oscillators architecture and current starved Voltage-controlled oscillators on the basis of (Power consumption, Phase-Noise, tunning range and supply voltage). Here state of art design of different ring oscillator are utilized to get comparative analysis for utilization in ultra wide band

关键词： Ring oscillators Wireless communication Frequency synthesizers Radiation effects Voltage-controlled oscillators Voltage performance analysis

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A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature

A Hardware-Software Co-Design for the Discrete Gaussian Samp...

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ieee International workshop on Hardware-Oriented Security and Trust (HOST)

作者： Emre Karabulut Aydin Aysu North Carolina State University NC USA

ISBN: (数字)9798350373943

ISBN: (纸本)9798350373950

Sampling random values from a discrete Gaussian distribution with high precision is a major and computationally-intensive operation of emerging and existing cryptographic standards. FALCON is one such algorithm that the National Institute of Standards and Technology chose to standardize as a next-generation, quantum-secure digital signature algorithm. The discrete Gaussian sampling of FALCON has both flexibility and efficiency needs–it constitutes 72% of total signature generation in reference software and requires sampling from a variable mean and standard deviation. Unfortunately, there are no prior works on accelerating this complete sampling procedure. In this paper, we propose a hardware-software co-design for accelerating FALCON's discrete Gaussian sampling subroutine. The proposed solution handles the flexible computations for setting the variable parameters in software and executes core operations with low latency, parameterized, and custom hardware. The hardware parameterization allows trading off area vs. performance. On a Xilinx SoC FPGA architecture, the results show that compared to the reference software, our solution can accelerate the sampling up to 56.05× and the full signature scheme by 1.67×. Moreover, we quantified that our optimized multiplier circuits can improve the throughput over a straightforward implementation by 2.87×.

关键词： Software algorithms NIST Throughput Software Hardware Low latency communication Standards

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high-performance GMRES Multi-Precision Benchmark: Design, performance, and Challenges

High-Performance GMRES Multi-Precision Benchmark: Design, Pe...

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International workshop on performance Modeling, Benchmarking and Simulation of high performance Computer Systems (PMBS)

作者： Ichitaro Yamazaki Christian Glusa Jennifer Loe Piotr Luszczek Sivasankaran Rajamanickam Jack Dongarra Sandia National Laboratories Albuquerque New Mexico USA University of Tennessee Knoxville Tennessee USA

ISBN: (纸本)9781665451864

We propose a new benchmark for high-performance (HP) computers. Similar to high performance Conjugate Gradient (HPCG), the new benchmark is designed to rank computers based on how fast they can solve a sparse linear system of equations, exhibiting computational and communication requirements typical in many scientific applications. The main novelty of the new benchmark is that it is now based on Generalized Minimum Residual method (GMRES) (combined with Geometric Multi-Grid preconditioner and Gauss-Seidel smoother) and provides the flexibility to utilize lower precision arithmetic. This is motivated by new hardware architectures that deliver lower-precision arithmetic at higher performance. There are other machines that do not follow this trend. However, using a lower-precision arithmetic reduces the required amount of data transfer, which alone could improve solver performance. Considering these trends, an HP benchmark that allows the use of different precisions for solving important scientific problems will be valuable for many different disciplines, and we also hope to promote the design of future HP computers that can utilize mixed-precision arithmetic for achieving high application performance. We present our initial design of the new benchmark, its reference implementation, and the performance of the reference mixed (double and single) precision Geometric Multi-Grid solvers on current top-ranked architectures. We also discuss challenges of designing such a benchmark, along with our preliminary numerical results using 16-bit numerical values (half and bfloat precisions) for solving a sparse linear system of equations.

关键词： Computers Linear systems Computational modeling Computer architecture Benchmark testing Market research Mathematical models

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A Comprehensive Evaluation of Novel AI Accelerators for Deep Learning Workloads

A Comprehensive Evaluation of Novel AI Accelerators for Deep...

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International workshop on performance Modeling, Benchmarking and Simulation of high performance Computer Systems (PMBS)

作者： Murali Emani Zhen Xie Siddhisanket Raskar Varuni Sastry William Arnold Bruce Wilson Rajeev Thakur Venkatram Vishwanath Zhengchun Liu Michael E. Papka Cindy Orozco Bohorquez Rick Weisner Karen Li Yongning Sheng Yun Du Jian Zhang Alexander Tsyplikhin Gurdaman Khaira Jeremy Fowers Ramakrishnan Sivakumar Victoria Godsoe Adrian Macias Chetan Tekur Matthew Boyd Argonne National Laboratory Lemont IL USA University of Illinois Chicago IL USA Cerebras Systems Sunnyvale CA USA SambaNova Systems Inc. Palo Alto CA USA Graphcore Inc. Palo Alto CA USA Groq Inc. Mountain View CA USA

ISBN: (纸本)9781665451864

Scientific applications are increasingly adopting Artificial Intelligence (AI) techniques to advance science. high-performance computing centers are evaluating emerging novel hardware accelerators to efficiently run AI-driven science applications. With a wide diversity in the hardware architectures and software stacks of these systems, it is challenging to understand how these accelerators perform. The state-of-the-art in the evaluation of deep learning workloads primarily focuses on CPUs and GPUs. In this paper, we present an overview of dataflow-based novel AI accelerators from SambaNova, Cerebras, Graphcore, and Groq. We present a first-of-a-kind evaluation of these accelerators with diverse workloads, such as Deep Learning (DL) primitives, benchmark models, and scientific machine learning applications. We also evaluate the performance of collective communication, which is key for distributed DL implementation, along with a study of scaling efficiency. We then discuss key insights, challenges, and opportunities in integrating these novel AI accelerators in supercomputing systems.

关键词： Deep learning Computational modeling high performance computing Conferences AI accelerators Full stack Computer architecture

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implementation and Evaluation of 5G MEC-enabled Smart Factory

Implementation and Evaluation of 5G MEC-enabled Smart Factor...

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ieee/ASME International Conference on Mechtronic and Embedded Systems and Applications, MESA

作者： Nadhif Muhammad Rekoputra Chia-Wei Tseng Jui-Tang Wang Shu-Hao Liang Ray-Guang Cheng Yueh-Feng Li Wen-Hao Yang Department of Electronic and Computer Engineering National Taiwan University of Science and Technology Taipei Taiwan Industry 4.0 Implementation Center National Taiwan University of Science and Technology Taipei Taiwan Wireless Communication Laboratory Telecommunication Laboratory of Chunghwa Telecom New Taipei City Taiwan

ISBN: (纸本)9781665455718

The 5G network can provide more comprehensive bandwidth connectivity for the industry 4.0 environment, which requires faster and tremendous data transmission. 5G network engages with Multi-access Edge Computing providing the computing functions dedicated to the users on edge nodes. The MEC network architecture presents the significant facilities, schematic of the network, and routers of data transmission. This work demonstrates the 5G network performance evaluation with MEC and without MEC and compares it with various wired and wireless networks in a machining workshop. The field test performs high-definition streaming video and heavy-traffic load testing to evaluate the performance based on different protocols by comparing throughput, latency, jitter, and packet loss rate. Streaming video performance shows that the 5G with MEC achieved 16.47 ms latency on average. In summary, the 5G network implementation and data transmission performance provide a paradigm for those interested. MEC can help data transmission efficiency, but it requires knowledge of configuration on optimization. Mobile network operators should offer authentication for accessing partial MEC functionality for industrial users.

关键词： performance evaluation 5G mobile communication Wireless networks Packet loss Streaming media Throughput Routing protocols

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