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ieee workshop on high performance Switching and Routing

作者： Jin-Cheol Kim Young-Hee Lee Information and Communications University Daejeon South Korea

Gaining lessons from the IntServ/RSVP experiences, more simplified differentiated services (DiffServ) has emerged as the core network architecture with enhanced scalability for implementation and deployment. In order to provision differentiated services on a DiffServ domain, it is necessary to provision resources appropriately in the control or management plane of the DiffServ domain, in addition to the data plane service protocols implementation. But, efforts in the control or management plane are not matured in the DiffServ domain. While the static provisioning may be sufficient for the quantitative traffic, the qualitative provisioning is more difficult to support, so that the provisioning parameters should be estimated based on the accurate traffic characteristics, which can be obtained from possibly real time measurements. The paper aims to resolve dynamic resource provisioning, especially for the qualitative traffic by measurement-based admission control scheme having some implicit signaling component using control plane DSCPs. The proposed scheme has been simulated on the ns-2 simulator, using traffic with burst characteristics. The results shows that the proposed scheme has the capability to support a fine-grained, dynamic admission control with flexibility in DiffServ domain.

关键词： Admission control Diffserv networks Traffic control Telecommunication traffic Resource management communication system traffic control Harmonic analysis Parameter estimation Signal resolution IP networks

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Towards high performance CORBA and MPI middlewares for grid computing 2nd

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2nd International workshop on Grid Computing, GRID 2001

作者： Denis, Alexandre Pérez, Christian Priol, Thierry IRISA/IFSIC Campus de Beaulieu Rennes Cedex35042 France IRISA/INRIA Campus de Beaulieu Rennes Cedex35042 France

ISBN: (纸本)3540429492

Due to the high level of heterogeneity in a computational Grid, designing a runtime system for such computing infrastructure is extremely challenging, for example regarding the ability to exploit transparently and efficiently various networking technologies. Programming a computational Grid often requires the use of several communication paradigms (RPC, RMI, DSM, Message passing) that have to share these networking resources. This paper presents the first step towards a runtime system that allows efficient communication for various communication-oriented middlewares. We introduce a CORBA implementation that reaches 240 MB/s, which is as far as we know the best CORBA performance. Thus, CORBA can be as efficient as MPI on high performance networks. Moreover, we show that different communication middlewares, like CORBA and MPI, can efficiently co-habit within the same runtime system taking full benefit of various networking resources (SAN to WAN). © Springer-Verlag Berlin Heidelberg 2001.

关键词： Common object request broker architecture (CORBA)

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Differentiated fairness: service model and implementation

Differentiated fairness: service model and implementation

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ieee workshop on high performance Switching and Routing

作者： B. Gaidioz P. Primet B. Tourancheau INRIA-ENS-Lyon RESAM-UCB-Lyon RESAM-EC-Lyon INRIA-ENS-Lyon France Sun Laboratories Europe USA

ISBN: (纸本)0780367111

Real-time traffic in the Internet is growing and the best-effort model has not been designed for such challenging streams. The DiffServ (DS) architecture, which permits one to aggregate traffic flows into classes with a common forwarding requirement, is a quality of service (QoS) solution for IP networks. But most of the DS models provide classes getting better performance than others, calling for pricing differentiation and possibly admission control. We explore the possibility of providing a simple, robust and pricing-free QoS solution by practising "differentiated fairness": different classes have equivalent performance according to their specific needs. No admission control is required, no absolute guarantee is provided. This "soft" model has been implemented and tested. Experiments shows that the scheduler can balance resource sharing so that "differentiated fairness" is obtained.

关键词： Quality of service Traffic control Admission control Telecommunication traffic Internet Diffserv networks Aggregates communication system traffic control IP networks Pricing

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Laurasia and Wind: a compiler-controlled software DSM for WS/PC clusters

Laurasia and Wind: a compiler-controlled software DSM for WS...

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International workshop on Innovative architecture for Future Generation high-performance Processors and Systems

作者： Uehara, T Saito, S Joe, K Kunieda, Y Wakayama Univ Fac Syst Engn Wakayama Japan

ISBN: (纸本)076950650X

We have proposed an approach to build an automatic parallelizing compiler for various parallel computer architectures by providing COMA (Cache-Only Memory architecture) environment that can be controlled by the compiler. This paper presents the design and implementation of a software DSM (Distributed Shared Memory) system named "Laurasia". It also describes a Low-Costs communication module named "Wind" which is developed to accelerate the performance of Laurasia. Laurasia is designed to run on a cluster of UNIX Workstations or PCs, and Wind is built in a Linux kernel to eliminate context switches between the kernel and the user process.

关键词： Laurasia Computer architecture Wind distributed shared memory systems Micro computer context switching

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Optimizing the parSOM neural network implementation for data mining with distributed memory systems and cluster computing 11

Optimizing the <i>par</i>SOM neural network implementation f...

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11th International workshop on Database and Expert Systems Applications

作者： Tomsich, P Rauber, A Merkl, D Vienna Univ Technol Inst Software Technol Vienna Austria

ISBN: (纸本)0769506801

The self-organizing map is a prominent unsupervised neural network model which lends itself to the analysis of high-dimensional input data and data mining applications. However the high execution times required to train the map put a limit to its application in many high-performance delta analysis application domains. In this paper Lye discuss the purSOM implementation, It software-based parallel implementation of rite self organizing map, and its optimization for the analysis of high-dimensional input data using distributed memory systems and clusters. The original purSOM algorithm scales very well bl a parallel execution environment with low communication latencies and exploits parallelism to cope with memory latencies. However it suffers from poor scalability on distributed memory couples. We present optimizations to further decouple the subprocesses, simplify the communication model and improve the portability of the system.

关键词： Application software Clustering algorithms Computer architecture Computer networks Data analysis Data mining Delay Neural networks Software libraries Time series analysis

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Spatio-temporal parallel processing and complexity reduction for OFDM multiple antennas system

Spatio-temporal parallel processing and complexity reduction...

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ieee workshop on Signal Processing Systems (SIPS)

作者： Tai-Lai Tung Kung Yao Dept. of Electr. Eng. California Univ. Los Angeles CA USA Electrical Engineering Department UCLA Los Angeles CA USA

In this paper, we propose combining spatio-temporal signal processing, OFDM technique and multiple antennas system for high data rate and high performance communication. In order to perform real time processing, we also propose a complexity-reduced QR-beamformer for VBLAST algorithm and parallel processing systolic array architectures. Simulations show that significant performance gains of the proposed system can be realized in terms of lower bit error rate and higher data transmission rate. Numerical evaluations also show that the proposed method and architectures can significantly save computational efforts and operational time.

关键词： Parallel processing Signal processing algorithms Computer architecture Array signal processing OFDM Systolic arrays Computational modeling performance gain Bit error rate Data communication

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Applicability of high level architecture (HLA) to distributed cooperative processing systems

Applicability of high level architecture (HLA) to distribute...

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1999 ieee International Conference on Systems, Man, and Cybernetics 'Human communication and Cybernetics'

作者： Furuichi, Masakazu Mizuno, Masaji Izumi, Hideyuki Ozaki, Atsuo Watanabe, Syusuke Tokumoto, Syuichi MITSUBISHI Electric Corp Kamakura Japan

This paper describes the recent R&D status of eRTI 1.3, the implementation of the principal functions of the high Level architecture Run Time Infrastructure (HLA-RTI) interface specification 1.3 (ieee 1516.1P) and its applicability to large scale distributed cooperative processing systems (DCOPS). In order to achieve flexibility and expandability for supporting large-scale distributed cooperative processing systems, standardized system architecture and interface to interconnect heterogeneous systems are mandatory. While the HLA is designed for providing the way to satisfy the above objective particularly for distributed simulation systems (DSS), its architecture and methodology are quite useful also for DCOPS. In this paper, we propose a DCOPS/HLA system architecture which utilizes HLA as a communication infrastructure for DCOPS. The system architecture of DCOPS and DSS are very similar from the RTI software design viewpoint. If we can show that the functions provided by the HLA are sufficient, and that the performance of infrastructure software is practical, the HLA can be applied to DCOPS. In this study, we focus on the performance issues. We first describe an overview of DCOPS/HLA architecture and our latest version of eRTI 1.3, then show the result of performance evaluation compared with the DMSO's (Defense Modeling and Simulation Office) RTI. The results indicate the upper bound of the communication frequency among agents and subsystems when DCOPS is implemented on the HLA.

关键词： Distributed computer systems

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An associative self-compacting buffer for communication switches 3

An associative self-compacting buffer for communication swit...

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3rd International workshop on Design of Mixed-Mode Integrated Circuits and Applications

作者： Delgado-Frias, J.G. Jafri, A. Dept. of Electr. Eng. State Univ. of New York BinghamtonNY13902-6000 United States

ISBN: (纸本)0780355881

This paper describes a novel VLSI CMOS implementation of a self-compacting buffer (SCB) for the dynamically allocated multi-queue (DAMQ) switch architecture. The SCB scheme dynamically allocates data regions within the input buffer for each output channel. The proposed scheme provides a high-performance solution to buffered communication switches that are required in interconnection networks. This performance comes from the DAMQ approach as well as the Associative Channel Pointer implementation and novel circuitry. The major components of the SCB are described in detail in this paper. The system has the capability of performing a read, a write, or a simultaneous read/write operation per cycle. © 1999 ieee.

关键词： Interconnection networks (circuit switching)

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3rd workshop on communication, architecture and Applications for Network-based Parallel Computing, CANPC 1999

3rd Workshop on Communication, Architecture and Applications...

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3rd International workshop on communication, architecture and Applications for Network-based Parallel Computing , CANPC 1999

ISBN: (纸本)3540659153

The proceedings contain 15 papers. The special focus in this conference is on Network-Based Parallel Computing. The topics include: A parallel implementation of the everglades landscape fire model in networks of workstations;adaptation models for network-aware distributed computations;prototyping execution models for HTMT petaflop machine in java;is it worth the flexibility provided by irregular topologies in networks of workstations;performance evaluation of the multimedia router with MPEG-2 video traffic;a scalable flow control algorithm for the fast messages communication library;high performance sockets and RPC over virtual interface VI architecture;the scheduled transfer ST protocol;the NIP parallel object-oriented computational model;support for scalable distributed shared objects;combining adaptive and deterministic routing;deadlock-free routing in irregular networks with dynamic reconfiguration;implementing application-specific cache-coherence protocols in configurable hardware;supporting shared memory and message passing on clusters of PCs with a SMiLE and low latency message-passing for reflective memory networks.

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Novel VLSI architecture for a variable-length key, 64-bit BLOWFISH block cipher

IEEE Workshop on Signal Processing Systems, SiPS: Design and...

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ieee workshop on Signal Processing Systems, SiPS: Design and implementation 1999年 568-577页

作者： Lai, Yeong-Kang Shu, Yu-Chuan Natl Dong-Hua Univ Taiwan

In this paper, a novel one-round VLSI architecture of the block cipher, BLOWFISH, for data encryption/decryption has been presented. Based on pipelined structure, efficient key management, and the mapping of the algorithm onto the datapath the performance of the architecture can be increased. In addition, all important standardized modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption like wireless communication applications.

关键词： Signal encoding

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