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ieee workshop on Signal Processing Systems, SiPS: Design and implementation 1999年 321-330页

作者： Dutta, Santanu Singh, Deepak Mehra, Vijay Philips Semiconductors Sunnyvale United States

This paper describes the architecture, functionality and design of TM-2700 - a digital television and media processor chip from Philips Semiconductors. The chip not only supports all eighteen digital television picture formats prescribed by the United States Advanced Television Systems Committee (ATSC), from standard-definition to wide-angle high-definition video, but has also the power to handle high-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2 video, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. TM-2700 is a programmable processor with a very powerful, general-purpose Very Long Instruction Word (VLIW) Central Processing Unit (CPU) core that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. Aided by an array of peripheral devices and high-performance buses, the CPU core facilitates concurrent processing of audio, video, graphics, and communication-data.

关键词： Image coding

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A low-power reconfigurable data-flow driven DSP system

A low-power reconfigurable data-flow driven DSP system

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ieee workshop on Signal Processing Systems (SIPS)

作者： M. Wan Hui Zhang M. Benes J. Rabaey Berkeley Wireless Research Center EECS Department University of California Berkeley USA

Reconfigurable architectures have emerged as a promising implementation platform to provide high-flexibility, high-performance, and low-power solutions for future wireless embedded devices. We discuss in details a reconfigurable data-flow driven architecture, including the computation model, communication mechanism, and implementation. We also describe a set of software tools developed to perform automatic mapping from algorithms to the architecture, as well as to evaluate the resulting performance and energy of the mapping. Finally, we present results on digital signal processing and wireless communication algorithms to show the energy efficiency of the system and the effectiveness of the tools. Our system shows more than one order of magnitude of improvement in terms of energy efficiency when compared to low-power programmable processors.

关键词： Digital signal processing Computer architecture Signal processing algorithms Energy efficiency Reconfigurable architectures Computational modeling Software tools performance evaluation Software algorithms Wireless communication

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A novel VLSI architecture for a variable-length key, 64-bit Blowfish block cipher

A novel VLSI architecture for a variable-length key, 64-bit ...

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ieee workshop on Signal Processing Systems (SIPS)

作者： Yeong-Kang Lai Yu-Chuan Shu Department of Computer Science and Information Engineering National Dong Hwa University Taiwan

A novel one-round VLSI architecture of the block cipher, Blowfish, for data encryption/decryption has been presented. Based on a pipelined structure, efficient key management, and the mapping of the algorithm onto the data path the performance of the architecture can be increased. In addition, all important standardised modes of operation of block ciphers, such as ECB, CBC, and OFB, are also supported. Due to the properties of low cost, high throughput rate, and scalable encryption, the VLSI block cipher provides efficient solutions for data encryption such as wireless communication application.

关键词： Very large scale integration Cryptography Wireless communication Computer architecture Throughput Protection Public key Data security Computer science Costs

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architecture and implementation of a single-chip programmable digital television and media processor

Architecture and implementation of a single-chip programmabl...

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ieee workshop on Signal Processing Systems (SIPS)

作者： S. Dutta D. Singh V. Mehra Philips Semiconductors Sunnyvale CA USA

This paper describes the architecture, functionality and design of TM-2700-a digital television and media processor chip from Philips Semiconductors. The chip not only supports all eighteen digital television picture formats prescribed by the United States Advanced Television Systems Committee (ATSC), from standard-definition to wide-angle high-definition video, but has also the power to handle high-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2 video, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. TM-2700 is a programmable processor with a very powerful, general-purpose Very Long Instruction Word (VLIW) Central Processing Unit (CPU) core that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. Aided by an array of peripheral devices and high-performance buses, the CPU core facilitates concurrent processing of audio, video, graphics, and communication-data.

关键词： HDTV high definition video Central Processing Unit Digital TV VLIW Decoding Multimedia systems System-on-a-chip Real time systems Operating systems

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The applicability of high level architecture (HLA) to distributed cooperative processing systems

The applicability of high level architecture (HLA) to distri...

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ieee International Conference on Systems, Man and Cybernetics

作者： M. Furuichi M. Mizuno H. Izumi A. Ozaki S. Watanabe S. Tokumoto Information Technology Research and Development Center Mitsubishi Electric Corporation Limited Kamakura Japan

This paper describes the R&D status of eRTI 1.3, the implementation of the principal functions of the high Level architecture Run Time Infrastructure (HLA-RTI) interface specification 1.3 (ieee 1516.1P) and its applicability to large scale distributed cooperative processing systems (DCOPS). In order to achieve flexibility and expandability for supporting DCOPS, standardized system architecture and interface to interconnect heterogeneous systems are mandatory. While the HLA is designed for providing the way to satisfy the above objective particularly for distributed simulation systems (DSS), its architecture and methodology are quite useful also for DCOPS. We propose a DCOPS/HLA system architecture which utilizes HLA as a communication infrastructure for DCOPS. The system architecture of DCOPS and DSS are very similar from the RTI software design viewpoint. If we can show that the functions provided by the HLA are sufficient, and that the performance of infrastructure software is practical, HLA can be applied to DCOPS. We focus on performance issues. We first give an overview of the DCOPS/HLA architecture and our latest version of eRTI 1.3, then show the results of performance evaluation compared with the DMSO's (Defense Modeling and Simulation Office) RTI. The results indicate the upper bound of the communication frequency among agents and subsystems when DCOPS is implemented on the HLA.

关键词： Computational modeling Computer architecture Delay Research and development Large-scale systems Decision support systems Frequency Application software Humans Traffic control

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Design of FLASH switch with flexible controllability

Design of FLASH switch with flexible controllability

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ieee workshop on ATM

作者： Kyeong Soo Kim Byung Do Ko Jae Geun Kim Jun Kyun Choi Switching and Transmission Technology Laboratory Electronics and Telecommunications Research Institute Taejon South Korea School of Communications Engineering Information and Communications University Taejon South Korea

We propose a new ATM switch with flexible buffering architecture and priority scheduling for providing a variety of QoS classes in this paper. In addition, this paper is concerned with the problem of supporting multiple QoS classes according to cell loss sensitivity and cell delay sensitivity. Loss-sensitive cells are given a higher priority to access a buffer with large free space to ensure a smaller cell loss probability, while delay-sensitive cells are assigned to a smaller buffer with high access priority to the output link to meet the shorter delay requirements. We also describe the implementation of a flexible ATM switch, FLASH (flexible ATM switch with high performance). FLASH also allows for multi-rate switching, supporting arbitrary-sized logical bit pipes with varying bandwidths. A notable characteristic is that FLASH provides multi-channel switching and guarantees cell sequence integrity without additional resequencing logic in the output port processors.

关键词： Switches Controllability Asynchronous transfer mode Delay communication switching Telecommunication switching Traffic control Job shop scheduling Bandwidth communication system traffic control

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A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

A high throughput rate and low circuit complexity QAM channe...

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ieee workshop on Signal Processing Systems (SIPS)

作者： Yin-Tsung Hwang Wei-Cheng Lin Department of Electronic Engineering National Yunlin University of Science and Technology Yunlin Taiwan

In this paper, a novel VLSI design for an all digital QAM channel equalizer is presented. We adopted a decision-feedback equalizer (DFE) structure to combat the inter-symbol-interference (ISI) induced during high speed data communication. The equalizer consists mainly of eight transversal adaptive filters and slicers. Since the adaptive filter along with the slicer will form a nonlinear feedback path, the resultant recursive computing often leads to a severe performance bottleneck. To overcome this, a bit serial, MSB first computing scheme based on distributed arithmetic and signed digit number system techniques was developed. In our scheme, the next symbol's equalization can be started as soon as the MSD of the current symbol is obtained. This leads to a computation overlap between successive symbol's equalization and can effectively improve the baud rate. The circuit complexity, however, is still kept low with the help of fine grain pipelining. With careful arrangement of data flow, an efficient systolic array design with 100% utilization and suitable for VLSI implementation is derived. The design architecture is also scalable in that the initiation interval between the processing of two consecutive symbols is a constant of 5+[m/4] clocks (in the delayed sign LMS case) and the hardware complexity is of order 2/spl middot/m/spl middot/(n+1), where m and n are tap order and word length.

关键词： Throughput Complexity theory Quadrature amplitude modulation Very large scale integration Decision feedback equalizers Adaptive filters Intersymbol interference Data communication Distributed computing Arithmetic

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Cross-platform analysis of fast messages for Myrinet 2nd

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2nd International workshop on communication, architecture, and Applications for Network-Based Parallel Computing (CANPC 98)

作者： Iannello, G Lauria, M Mercolino, S Univ Naples Federico II Dipartimento Informat & Sistemist I-80125 Naples Italy

ISBN: (纸本)3540641408

Designing high performance communication software requires an in-depth understanding of the role of the components of the underlying machine/network architecture and their reciprocal interactions. The task is complicated by the continuing technological advances in the machine architectures. In this paper we analyze the performance of the Fast Messages (FM) high performance messaging layer on three platforms as different as a Spare 5, a Ultra 1, and a PentiumPro PC. Using a characterization in terms of the LogP model, me expose how the differences in the machine architectures are reflected in the way the different parts of a communication library like FM behaves and how their reciprocal interaction is affected. Our work shows that the FM implementation is "robust", tolerating large variations of machine performance while preserving the basic balances of its design. It also shows that a properly extended LogP model can be an invaluable architectural analysis tool.

关键词： Network architecture

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Implementing protected multi-user communication for Myrinet 2nd

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2nd International workshop on communication, architecture, and Applications for Network-Based Parallel Computing (CANPC 98)

作者： Nagar, S Seed, D Sivasubramaniam, A Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)3540641408

A Network of Workstations (NOW) is emerging as a cost-effective solution to high performance computing. However, we need to lower the cost of communicating between the workstations to make this platform viable. With the advent of high-performance networks such as ATM and Myrinet, the physical network is no longer the communication bottleneck. Rather, the major overhead can now be attributed to software. This overhead is a direct result of the cost that a message incurs as it travels through different protection domains. We can alleviate this problem by allowing protected user-level access directly to the network, thereby eliminating the kernel from the critical path. This paper presents a description of the design, implementation and performance of a protected user-level messaging system over Myrinet, called MU-Net, that can handle multiple application processes concurrently. MU-Net has been implemented on the SUN Solaris 2.5 operating system.

关键词： Computers

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Semi-automated design of high-performance communication subsystems

Semi-automated design of high-performance communication subs...

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The 1998 31st Annual Hawaii International Conference on System Sciences, HICSS-31

作者： Schiller, Jochen H. Carle, Georg J. Univ of Karlsruhe Karlsruhe Germany

implementations of communication protocols are typically based on highly specialized components, e.g., VLSI chips for ATM Adaptation Layer processing. The development of these specialized implementations is very time-consuming and, thus, justified only for high volumes. For a large number of multimedia applications, it would be desirable to be able to provide quickly high-performance implementations of protocols with new functionality. Using a unifying design method and suitable design tools, this goal can be achieved today. Our solution is based on a standard language for protocol specification, a generic target architecture for protocol implementation, and customized/commercial tools for mapping of the protocol specification onto the target platform. Using this approach for a powerful ATM Adaptation Layer protocol featuring forward error correction and retransmission we demonstrate the applicability for complex protocols with stringent timing requirements. Additionally, our approach results in fairly small hardware solutions compared to common processors.

关键词： Data communication systems

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