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An Atm Network Interface for high-Speed Experimentation

An Atm Network Interface for High-Speed Experimentation

引用

ieee workshop on the architecture and implementation of high performance communication subsystems

作者： B.S. Davie Bell Communications Research Inc. Morristown NJ USA

To connect host computers to an Asynchronous Transfer Mode (ATM) network, a network interface is required. The interface must be able to move data between the network and the host and to convert between the data format used in the network (ATM cells) and that used in the host (eg. variable length protocol data units). In the work described here, the goal was to prototype such an interface and to satisfy two contradictory requirements: speed of operation and flexibility to support experimentation. To achieve this goal, we defined an architecture which uses microprocessors for those functions where most flexibility is required, such as the execution of Segmentation and Reassembly (SAR) algorithms, while more specialized hardware is used for critical high-speed functions such as data movement and formatting of ATM cells. The details of this architecture are described and the results that have been obtained so far with the experimental prototype implementation are presented.

关键词： Network interfaces Asynchronous transfer mode Computer networks Computer interfaces Prototypes Workstations Protocols high-speed networks Bandwidth Microprocessors

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A VLSI ATM Cell Processor for Broadband Network subsystems

A VLSI ATM Cell Processor for Broadband Network Subsystems

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ieee workshop on the architecture and implementation of high performance communication subsystems

作者： J.J. Hickey Bell Communications Research Inc. Morristown NJ USA

Broadband networks are designed for high-bandwidth time-sensitive traffic at speeds more than 10 times the speed of networks today. These speeds place extraordinary stress on the network sabsystems. Typically, subsystems designed for use in the broadband network make use of specialized hardware to provide necessary throughput. Such hardware is usually very restrictive in the types of traffic it can handle. New traffic types often requires changes in the hardware, which increases the cost and design time. To generalize the network interface hardware, we designed a special purpose experimental RISC processor in VLSI with an optimized instruction set, and on-board network communication interfaces. Network data are processed entirely on-chip under the control the the processing unit. The number of traffic types that can be handled is limited only by the time it takes to process the traffic type. This processor is intended for use in experimental broadband networks at speeds of 155-622 Mbps.

关键词： Very large scale integration Broadband communication Hardware Network interfaces communication system traffic control Microprocessors communication system control Protocols ISDN Bandwidth

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A Subcarrier Multiplexed Network (scm-Net) architecture for Multigigabit/Second Heterogeneous Data Transmission

A Subcarrier Multiplexed Network (scm-Net) Architecture for ...

引用

ieee workshop on the architecture and implementation of high performance communication subsystems

作者： A.R. Bugos R. Olshansky GTE Laboratories Inc. USA

The basic architecture of a multigigabit per second local area network which utilizes a subcarrier multiplexed optical carrier to provide multiple asynchronous information channels is described. The network is design for high-capacity transmission of data, voice, and video traffic simultaneously using variable-length datagrams, ATM-cells, and circuit-switched video. Multi-user access to the information channels is provided through a separate control channel which uses a simple "token passing" protocol. A significant advantage of the SCM-NET design is that medium-speed node controllers operating at roughly 25 MHz can efficiently control several gigabits of information per second through switched access to the various subcarrier multiplexed channels.

关键词： Optical fiber networks Optical fibers WDM networks Baseband Fault tolerance Asynchronous transfer mode Optical receivers Optical transmitters Circuits Optical variables control

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A Host Interface to the Dtm high Speed Network

A Host Interface to the Dtm High Speed Network

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ieee workshop on the architecture and implementation of high performance communication subsystems

作者： B. AhIgren Swedish Institute of Computer Science Sweden

DTM dynamic synchronous transfer mode, is a new time division multiplexing technique for fiber networks currently being developed and implemented at the Royal Institute of Technology in Stockholm, Sweden. This paper describes the hardware and software aspects of the design of a SBus host interface to the DTM network for a Sun SPARCstation. The interface is based on a dual ported shared memory residing on the interface card and accessible over the SBus from the host CPU. The host operating system allocates message buffers directly in this memory. The interface has hardware support for segmenting and reassembling packets to and from the data units of the DTM. The software part of the interface manages the shared memory and the virtual circuits provided by the DTM network.

关键词： high-speed networks Hardware Sun Bandwidth Optical fiber devices Kernel Throughput Central Processing Unit Operating systems Memory management

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XTP specification and parallel implementation

XTP specification and parallel implementation

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1992 ieee International workshop on Advanced communications and Applications for high Speed Networks, IWACA 1992

作者： Heinrichs, Bernd Aachen University of Technology Lehrstuhl für Informatik IV Ahornstr. 55 AachenD-5100 Germany

ISBN: (纸本)078030764X

Future communication systems will consist of a large number of heterogeneous protocol worlds. In order to optimize the performance of all different protocol stacks, general purpose controller architectures should be used besides special protocol machines. Regardit g this issue we present our own software implementation strategy based on a dedicated controller architecture supporting versatile protocol processing. We use a programming language based on high level Petri nets, since Petri nets are well suited to describe protocol inherent parallelism and to fix the desired granularity of the implementation. Petri nets are also preferred since they are a description means which brings formal specification techniques together with a highly efficient concurrent execution of the protocol software. To demonstrtte the functionality of our implementation method the Xpres s Transfer Protocol (XTP) is specified with high level Petri nets and the straightforward way to achieve a parallel implementation is illustrated. © 1992 ieee.

关键词： Petri nets

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The fair distributed queue protocol for high speed networking

The fair distributed queue protocol for high speed networkin...

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ieee workshop on the architecture and implementation of high performance communication subsystems

作者： M. Kabatepe K.S. Vastola Electrical Computer and Systems Engineering Depstrtment Rensselaer Polytechnic Institute Troy NY USA

Advances in fiber optic technology now allow networks to opeozate at transmission rates greater than one gigabit per second (1Gb/s). The increase in network perfonnance promises the potential for supporting applications that require high bandwidth, low latency and predictable performance. However, the benefits to the transfer of bits node-to-node are limited. Latencies inside the nodes in the form of pocessiog delays and access delays remain the two "bottlenecks" that restrict end-to-end performance. Here, we address the second bottleneck. We consider a very efficient protocol called Fair Distributed Queue (FDQ), suitable for very high speed networts over lang distances. It uses the fiber optic medium and utilizes the full channel capacity indepmdent of the network length, the transmission speed and the number of nodes. Hence, it offers the high bandwidth required by future networks. FDQ's topology and certain other features are related to DQDB. However, it does not suffer from the asymmetry problems usociated with DQDB. The DQDB protocol has recently been accepted as the ieee 802.6 Standard for metropolitan area networks (MANs). The purpose of this sbort paper is to summarize some of the results from, especially regarding high bandwidth implementations. We show that FDQ has lower average delay results under Poisson load than both DQDB and DQDB with BWB. Also, its worst-case delay performance for messages (assuming messages require a multiple number of slots to be transmitted) is significantly better than DQDB with or without BWB. Thus, it meets low latency requirements in addition to high bandwidth. FDQ's scalability properties allow its total length to extend over 100 Ian and transmission rates well above 1 Gb/s. This eliminates the upward mobility problems faced by current network protocols, including DQDB.

关键词： Protocols high-speed networks Bandwidth Delay Network topology Optical fibers FDDI Systems engineering and theory Channel capacity Data structures

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Parallelism and performance in communication subsystems

Parallelism and performance in communication subsystems

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ieee workshop on Future Trends of Distributed Computing Systems

作者： S.-P. Chang A. Tantawy H. Meleis IBM Research Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA

This paper discusses the impact of various design and implementation factors on the performance of a communication subsystem. Measurements obtained from two different software implementations of the same protocol (ISO 8802-2 logical link control protocol type 2) over three different experimental hardware platforms are used as a basis for comparison. The impact of exploiting parallelism is especially emphasized. The effects of software structure and optimized hand coding are also discussed. Although some results pertain to only one specific protocol, similarities with other connection-oriented protocols can be drawn.< >

关键词： Hardware Computer architecture Media Access Protocol Access protocols Software prototyping Prototypes FDDI Software measurement communication system control high-speed networks

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high-speed VLSI pipelined processor design for lossless image data compression 6

High-speed VLSI pipelined processor design for lossless imag...

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6th ieee workshop on VLSI Signal Processing

作者： Fang, Wai-Chi Sheu, Bing J. Radar Science and Engineering Jet Propulsion Laboratory California Institute of Technology PasadenaCA91109-8099 United States Signal and Image Processing Institute Department of Electrical Engineering University of Southern California Los AngelesCA90089-0271 United States

ISBN: (纸本)0780308115

An efficient VLSI pipelined processor design for high-speed lossless compression based on "Rice algorithm" has been developed to meet the increasing strong demands on high-volume/high-speed image data communication and storage. The Rice algorithm is an adaptive lossless coding scheme that provides near-optimal performance over a broad range of data entropies. The Rice algorithm is also an efficiently implementable scheme for VLSI realization. A VLSI pipelined architecture was developed to allow compact implementation of a single-chip VLSI compressor. This lossless compressor is named PSI14,K+ since it implements an advanced version of the Rice's universal noiseless coding method called PSI14,K+. The chip layout was generated for a 1.0- micron CMOS technology. It occupies a compact chip area of 5.1 × 5.3 mm2, with 49,000 transistors, 57 input/output pads, and 6 power/ground pads. The total power dissipation is 0.4 watts at the 40 MHz system clock with a 50% switching duty cycle. This compressor chip is mounted in a 68-pin pin-grid-array package. It can operate up to 40 Mpixels/sec. The potential applications of the proposed lossless compressor include database management systems, scientific instruments, CAE workstations, desktop computing machines, and the data systems that require highspeed compression without fidelity loss. © 1992 ieee.

关键词： Compressors

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MasPar MP-1 architecture

MasPar MP-1 architecture

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Digest of Papers - Thirty-Fifth ieee Computer Society International Conference - COMPCON Spring '90

作者： Blank, Tom MasPar Computer Corp Sunnyvale CA USA

ISBN: (纸本)0818620285

The MasPar MP-1 architecture is described. It is a massively parallel SIMD (single-instruction, multiple-data) machine with the following key characteristics: scalable architecture in terms of the number of processing elements, system memory, and system communication bandwidth;reduced-instruction-set-computer- (RISC-) like instruction set design which leverages optimizing compiler technology;adherence to industry-standard floating point formats, specifically VAX and ieee floating point;and an architectural design amenable to a VLSI implementation. The architecture provides not only high computational capability, but also a mesh and global interconnect style of communication. The computational model and subsystems of the MP-1, including the interconnection mechanisms, are described. Companion papers describe the software system and provide a description of the hardware implementation. A key attribute of the MP-1 system architectures is that the system characteristics are all scalable. Specifically, as the performance increases (more processing element boards are added), the system memory and the communications bandwidth increase.

关键词： Computer architecture

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Efficient interprocessor communication in a tightly-coupled homogeneous multiprocessor system

Efficient interprocessor communication in a tightly-coupled ...

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Proceedings of the 2nd ieee workshop on Future Trends of Distributed Proceedings of the 2nd ieee workshop on Future Trends of Distributed Computing Systems - Future Trends 90 Computing Systems - Future Trends 90

作者： van der Wal, A.J. van Dijk, G.J.W. Dept of Phys Eindhoven Univ of Technol Netherlands

ISBN: (纸本)0818620889

The authors illustrate the importance of using a system-oriented approach in developing a multiprocessor architecture. The study concerns the implementation of interprocessor communication in the Eindhoven Multiprocessor System (EMPS). In the EMPS a truly distributed interrupt mechanism is available to operating system primitives for message passing and remote procedure calls. The distributed interrupt mechanism for interprocessor communication that is implemented in the EMPS avoids the problem of bus contention by interrupts. By using an interactive approach between hardware and software design a modular, flexible, and yet high-performance system is realized. performance measurements of message passing and remote procedure calls, which exploit the mechanism of distributed interrupts, are presented.

关键词： Computer Systems, Digital

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