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Design and performance evaluation of a NoC-based router architecture for MPSoC

Design and performance evaluation of a NoC-based router arch...

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4th International Conference on Computational Intelligence and communication Networks, CICN 2012

作者： Shrivastava, Anurag Pandit, Amit Kant School of ECE Shri Mata Vaishno Devi University Katra Jammu India

ISBN: (纸本)9781467329811

NOC is an approach in designing communication subsystems between intelligent property (IP) cores in SOC with greater efficiency. Packet switched network are being proposed as global communication architecture for future soc designs and implementation. For effective global on-chip communication, on-chip routers provide expected routing functionality with low complexity and better performance. This paper provides Analytical Design and implementation of on-chip router architecture for MPSOC, which is the concept of high efficiency architectural design. © 2012 ieee.

关键词： Network-on-chip

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Designing Scalable PGAS communication subsystems on Cray Gemini Interconnect

Designing Scalable PGAS Communication Subsystems on Cray Gem...

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19th International Conference on high performance Computing (HiPC)

作者： Vishnu, Abhinav Daily, Jeff Palmer, Bruce Pacific Northwest Natl Lab 902 Battelle Blvd Richland WA 99352 USA

ISBN: (纸本)9781467323703;9781467323727

The Cray Gemini Interconnect has been recently introduced as a next generation network architecture for building multi-petaflop supercomputers. Cray XE6 systems including LANL Cielo, NERSC Hopper, and the proposed NCSA Blue-Waters, as well as the Cray XK6 ORNL Titan leverage the Gemini Interconnect as their primary Interconnection network. At the same time, programming models such as the Message Passing Interface (MPI) and Partitioned Global Address Space (PGAS) models such as Unified Parallel C (UPC) and Co-Array Fortran (CAF) have become available on these systems. Global Arrays is a popular PGAS model used in a variety of application domains including hydrodynamics, chemistry and visualization. Global Arrays uses Aggregate Remote Memory Copy Interface (ARMCI) as the communication runtime system for Remote Memory Access (RMA) communication. This paper presents a design, implementation and performance evaluation of scalable and high performance communication ARMCI on Cray Gemini. The design space is explored and time-space complexities of communication protocols for one-sided communication primitives such as contiguous and uniformly non-contiguous datatypes, atomic memory operations (AMOs) and memory synchronization is presented. An implementation of the proposed design (referred as ARMCI-Gemini) demonstrates the efficacy on communication primitives, application kernels such as LU decomposition and applications such as Smooth Particle Hydrodynamics (SPH).

关键词： application program interfaces computational complexity message passing parallel processing protocols

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A novel virtual channel implementation technique for multi-core on-chip communication

A novel virtual channel implementation technique for multi-c...

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3rd workshop on Applications for Multi-Core architecture, WAMCA 2012

作者： Gharan, Masoud Oveis Khan, Gul N. Electrical and Computer Engineering Department Ryerson University Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781467350259

In this paper, a new approach for implementing virtual channels (VC) for multi-core interconnection networks is presented. In this approach, the flits of different packets interleave in a channel with a single buffer of nominal depth by using a rotating flit-by-flit arbitration. The routing path of each flit is guaranteed because the flits belonging to the same packet are attached with an ID tag at each router so that they are differentiable at downstream routers. We present this on-chip communication of packets through sharing of channel and buffer, which is a novel method of virtual channel implementation. Furthermore, we demonstrate it by adding arbitrary virtual channels depending on the number of packet requests for a physical channel. In this way, NoC (Network-on-Chip) contention can be removed cheaply. Moreover, we discuss contention free communication where the depth of shared buffer does not affect the performance. A contention-free communication with small (one) buffer depth can create an efficient on-chip communication with high performance, small chip area and low power consumption. © 2012 ieee.

关键词： Routers

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An Efficient Framework for Multi-dimensional Tuning of high performance Computing Applications

An Efficient Framework for Multi-dimensional Tuning of High ...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Cong, Guojing Wen, Huifang Chung, I-hsin Klepacki, David Murata, Hiroki Negishi, Yasushi IBM TJ Watson Res Ctr 1101 Kitchawan Rd Yorktown Hts NY 10598 USA IBM Tokyo Res Lab Tokyo Japan

ISBN: (纸本)9780769546759

Deploying an application onto a target platform for high performance oftentimes demands manual tuning by experts. As machine architecture gets increasingly complex, tuning becomes even more challenging and calls for systematic approaches. In our earlier work we presented a prototype that combines efficiently expert knowledge, static analysis, and runtime observation for bottleneck detection, and employs refactoring and compiler feedback for mitigation. In this study, we develop a software tool that facilitates fast searching of bottlenecks and effective mitigation of problems from major dimensions of computing (e. g., computation, communication, and I/O). The impact of our approach is demonstrated by the tuning of the LBMHD code and a Poisson solver code, representing traditional scientific codes, and a graph analysis code in UPC, representing emerging programming paradigms. In the experiments, our framework detects with a single run of the application intricate bottlenecks of memory access, I/O, and communication. Moreover, the automated solution implementation yields significant overall performance improvement on the target platforms. The improvement for LBMHD is upto 45%, and the speedup for the UPC code is upto 5. These results suggest that our approach is a concrete step towards systematic tuning of high performance computing applications.

关键词： high performance Computing Traffic Bottlenecks tuning Software Tools manual tuning Codes performance boost Expert Opinion Speeding IO Frameworks machine architectures

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Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

Hardware-assisted Decentralized Resource Management for Netw...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Heisswolf, Jan Zaib, Aurang Weichslgartner, Andreas Koenig, Ralf Wild, Thomas Teich, Juergen Herkersdorf, Andreas Becker, Juergen Karlsruhe Inst Technol Karlsruhe Germany Tech Univ Munich Munich Germany Univ Erlangen Nurnberg Erlangen Germany

ISBN: (纸本)9780769546766

Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is required that ensures fair sharing of communication resources between applications. Decentralized strategies provide better scalability in many-core systems. In this paper, we propose a hardware supported decentralized NoC resource management strategy. Our concept enables to define NoC regions through decentralized reconfigurable resource management policies. It offers improved performance and communication resource allocation within the regions. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance benefit within the region and the increased probability for successful reservation of communication resources. implementation results show the low area overhead of the proposed hardware support.

关键词： communication resources management of resources Quality of service Decentralized network-on-chip Scalability Computer hardware Simulation results

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FPGA implementation of ZF-THP for MU-MISO-OFDM systems 17

FPGA implementation of ZF-THP for MU-MISO-OFDM systems

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17th International OFDM workshop 2012, InOWo 2012

作者： Ludwig, Frank Budweg, Axel Paul, Steffen University of Bremen Bremen28359 Germany

ISBN: (纸本)9783800733606

In wireless multi-user communication systems with multi-antenna base stations the application of precoding techniques is strongly recommended for accurate detection of the signals at the mobile stations if no cooperation between them is desired. The Tomlinson-Harashima Precoding (THP) for MIMO channels provides an excellent performance combined with low complexity at the receivers. In this contribution an efficient FPGA implementation of Zero-Forcing THP is presented. It is well suited for the modular architecture of base stations. A high throughput is achieved by parallelization and pipelining. The developed fixed-point design obtains the same bit error rate performance as an ideal floating-point precoding. © 2012 VDE Verlag GmbH. All rights reserved.

关键词： Base stations

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Design of Direct communication Facility for Many-Core based Accelerators

Design of Direct Communication Facility for Many-Core based ...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Si, Min Ishikawa, Yutaka Univ Tokyo Dept Comp Sci Tokyo Japan

ISBN: (纸本)9780769546766

A direct communication facility, called DCFA, for a many-core based cluster, whose compute node consists of many-core units connected to the host via PCI Express with Infiniband, is designed and evaluated. Because a many-core unit is a device of the PCI Express bus, it is not capable of configuring and initializing the Infiniband HCA, according to the PCI Express specification. This means that the host has to assist memory transfer between many-core units, and thus extra communication overhead is incurred. In DCFA, the internal structures of the Infiniband HCA are distributed to both the memory space of the host and that of the many-core unit. After the host CPU configures and initializes the HCA, it obtains the addresses of both the HCA and the internal structures assigned by the host. Using the information given by the host and the internal structures assigned in the many-core memory area, the many-core unit may transfer data directly between other many-core units using the HCA without host assists. The implementation of DCFA is based on the Mellanox Infiniband HCA and Intel's Knights Ferry. Preliminary results show that, for large data transfer, the latency of DCFA delivers the same performance as that of host to host data transfer.

关键词： cluster direct communication many-core infiniband accelerator

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Hierarchical QR factorization algorithms for multi-core cluster systems

Hierarchical QR factorization algorithms for multi-core clus...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Dongarra, Jack Faverge, Mathieu Herault, Thomas Langou, Julien Robert, Yves Univ Tennessee Knoxville Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England Univ Colorado Denver CO USA Ecole Normale Superieure Lyon Lyon France

ISBN: (纸本)9780769546759

This paper describes a new QR factorization algorithm which is especially designed for massively parallel platforms combining parallel distributed multi-core nodes. These platforms make the present and the foreseeable future of high-performance computing. Our new QR factorization algorithm falls in the category of the tile algorithms which naturally enables good data locality for the sequential kernels executed by the cores (high sequential performance), low number of messages in a parallel distributed setting (small latency term), and fine granularity (high parallelism). Each tile algorithm is uniquely characterized by its sequence of reduction trees. In the context of a cluster of multicores, in order to minimize the number of inter-processor communications (aka, "communication-avoiding" algorithm), it is natural to consider two-level hierarchical trees composed of an "inter-node" tree which acts on top of "intra-node" trees. At the intra-node level, we propose a hierarchical tree made of three levels: (0) "TS level" for cache-friendliness, (1) "low level" for decoupled highly parallel inter-node reductions, (2) "coupling level" to efficiently resolve interactions between local reductions and global reductions. Our hierarchical algorithm and its implementation are flexible and modular, and can accommodate several kernel types, different distribution layouts, and a variety of reduction trees at all levels, both inter-cluster and intra-cluster. Numerical experiments on a cluster of multicore nodes (1) confirm that each of the four levels of our hierarchical tree contributes to build up performance and (2) build insights on how these levels influence performance and interact within each other. Our implementation of the new algorithm with the DAGUE scheduling tool significantly outperforms currently available QR factorization softwares for all matrix shapes, thereby bringing a new advance in numerical linear algebra for petascale and exascale platforms.

关键词： QR factorization numerical linear algebra hierarchical architecture distributed memory cluster multicore

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A Fast Parallel implementation of Molecular Dynamics with the Morse Potential on a Heterogeneous Petascale Supercomputer

A Fast Parallel Implementation of Molecular Dynamics with th...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Wu, Qiang Yang, Canqun Wang, Feng Xue, Jingling Natl Univ Def Technol Sch Comp Sci Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9780769546766

Molecular Dynamics (MD) simulations have been widely used in the study of macromolecules. To ensure an acceptable level of statistical accuracy relatively large number of particles are needed, which calls for high performance implementations of MD. These days heterogeneous systems, with their high performance potential, low power consumption, and high price-performance ratio, offer a viable alternative for running MD simulations. In this paper we introduce a fast parallel implementation of MD simulation with the Morse potential on Tianhe-1A, a petascale heterogeneous supercomputer. Our code achieves a speedup of 3.6x on one NVIDIA Tesla M2050 GPU (containing 14 Streaming Multiprocessors) compared to a 2.93GHz six-core Intel Xeon X5670 CPU. In addition, our code runs faster on 1024 compute nodes (with two CPUs and one GPU inside a node) than on 4096 GPU-excluded nodes, effectively rendering one GPU more efficient than six six-core CPUs. Our work shows that large-scale MD simulations can benefit enormously from GPU acceleration in petascale supercomputing platforms. Our performance results are achieved by using (1) a patch-cell design to exploit parallelism across the simulation domain, (2) a new GPU kernel developed by taking advantage of Newton's Third Law to reduce redundant force computation on GPUs, (3) two optimization methods including a dynamic load balancing strategy that adjusts the workload, and a communication overlapping method to overlap the communications between CPUs and GPUs.

关键词： Molecular Dynamics heterogeneous computing petascale supercomputer GPU computing

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Mapping Dense LU Factorization on Multicore Supercomputer Nodes

Mapping Dense LU Factorization on Multicore Supercomputer No...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Lifflander, Jonathan Miller, Phil Venkataraman, Ramprasad Arya, Anshu Kale, Laxmikant Jones, Terry Univ Illinois Urbana IL 61801 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9780769546759

Dense LU factorization is a prominent benchmark used to rank the performance of supercomputers. Many implementations use block-cyclic distributions of matrix blocks onto a two-dimensional process grid. The process grid dimensions drive a trade-off between communication and computation and are architecture-and implementation-sensitive. The critical panel factorization steps can be made less communication-bound by overlapping asynchronous collectives for pivoting with the computation of rank-k updates. By shifting the computation-communication trade-off, a modified block-cyclic distribution can beneficially exploit more available parallelism on the critical path, and reduce panel factorization's memory hierarchy contention on now-ubiquitous multicore architectures. During active panel factorization, rank-1 updates stream through memory with minimal reuse. In a column-major process grid, the performance of this access pattern degrades as too many streaming processors contend for access to memory. A block-cyclic mapping in the row-major order does not encounter this problem, but consequently sacrifices node and network locality in the critical pivoting steps. We introduce striding to vary between the two extremes of row-and column-major process grids. The maximum available parallelism in the critical path work (active panel factorization, triangular solves, and subsequent broadcasts) is bounded by the length or width of the process grid. Increasing one dimension of the process grid decreases the number of distinct processes and nodes in the other dimension. To increase the harnessed parallelism in both dimensions, we start with a tall process grid. We then apply periodic rotation to this grid to restore exploited parallelism along the row to previous levels. As a test-bed for further mapping experiments, we describe a dense LU implementation that allows a block distribution to be defined as a general function of block to processor. Other mappings can be tested with only

关键词： grids factorization Grid Lutetium Pivot Device Component Synclitism parallelism supercomputer MAPPING(MATHEMATICAL) Multi-core processors architecture Ganglia dimensions

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