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Sparse matrix-vector multiplication on GPGPU clusters: A new storage format and a scalable implementation

Sparse matrix-vector multiplication on GPGPU clusters: A new...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Kreutzer, Moritz Hager, Georg Wellein, Gerhard Fehske, Holger Basermann, Achim Bishop, Alan R. Erlangen Reg Comp Ctr Erlangen Germany Ernst Moritz Univ Greifswald D-17487 Greifswald Germany German Aerosp Ctr Dlr Simulat & Software Technol Cologne Germany Los Alamos Natl Lab Theory Simulat & Computat Directorate Los Alamos NM USA

ISBN: (纸本)9780769546766

Sparse matrix-vector multiplication (spMVM) is the dominant operation in many sparse solvers. We investigate performance properties of spMVM with matrices of various sparsity patterns on the nVidia "Fermi" class of GPGPUs. A new "padded jagged diagonals storage" (pJDS) format is proposed which may substantially reduce the memory overhead intrinsic to the widespread ELLPACK-R scheme while making no assumptions about the matrix structure. In our test scenarios the pJDS format cuts the overall spMVM memory footprint on the GPGPU by up to 70%, and achieves 91% to 130% of the ELLPACK-R performance. Using a suitable performance model we identify performance bottlenecks on the node level that invalidate some types of matrix structures for efficient multi-GPGPU parallelization. For appropriate sparsity patterns we extend previous work on distributed-memory parallel spMVM to demonstrate a scalable hybrid MPI-GPGPU code, achieving efficient overlap of communication and computation.

关键词： GPGPU Sparse matrices CUDA

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Optimizing MPI communication on Multi-GPU Systems using CUDA Inter-Process communication

Optimizing MPI Communication on Multi-GPU Systems using CUDA...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Potluri, S. Wang, H. Bureddy, D. Singh, A. K. Rosales, C. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Texas Adv Comp Ctr Austin TX 78758 USA

ISBN: (纸本)9780769546766

Many modern clusters are being equipped with multiple GPUs per node to achieve better compute density and power efficiency. However, moving data in/out of GPUs continues to remain a major performance bottleneck. With CUDA 4.1, NVIDIA has introduced Inter-Process communication (IPC) to address data movement overheads between processes using different GPUs connected to the same node. State-of-the-art MPI libraries like MVAPICH2 are being modified to allow application developers to use MPI calls directly over GPU device memory. This improves the programmability for application developers by removing the burden of dealing with complex data movement optimizations. In this paper, we propose efficient designs for intra-node MPI communication on multi-GPU nodes, taking advantage of IPC capabilities provided in CUDA. We also demonstrate how MPI one-sided communication semantics can provide better performance and overlap by taking advantage of IPC and the Direct Memory Access (DMA) engine on a GPU. We demonstrate the effectiveness of our designs using microbenchmarks and an application. The proposed designs improve GPU-to-GPU MPI Send/Receive latency for 4MByte messages by 79% and achieve 4 times the bandwidth for the same message size. One-sided communication using Put and Active synchronization shows 74% improvement in latency for 4MByte message, compared to the existing Send/Receive based implementation. Our benchmark using Get and Passive Synchronization demonstrates that true asynchronous progress can be achieved using IPC and the GPU DMA engine. Our designs for two-sided and one-sided communication improve the performance of GPULBM, a CUDA implementation of Lattice Boltzmann Method for multiphase flows, by 16%, compared to the performance using existing designs in MVAPICH2. To the best of our knowledge, this is the first paper to provide a comprehensive solution for MPI two-sided and one-sided GPU-to-GPU communication within a node, using CUDA IPC.

关键词： integrated pollution control communication Research application developer Line of nodes programmability GRAPPER PICK UP lattice Boltzmann methods

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Holistic Debugging of MPI Derived Datatypes

Holistic Debugging of MPI Derived Datatypes

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Protze, Joachim Hilbrich, Tobias Knuepfer, Andreas de Supinski, Bronis R. Mueller, Matthias S. Tech Univ Dresden Ctr Informat Serv & High Performance Comp Dresden Germany Ctr Appl Sci Comp LLNL Livermore CA 94550 USA

ISBN: (纸本)9780769546759

The Message Passing Interface (MPI) specifies an API that allows programmers to create efficient and scalable parallel applications. The standard defines multiple constraints for each function parameter. For performance reasons, no MPI implementation checks all of these constraints at runtime. Derived datatypes are an important concept of MPI and allow users to describe an application's data structures for efficient and convenient communication. Using existing infrastructure we present scalable algorithms to detect usage errors of basic and derived MPI datatypes. We detect errors that include constraints for construction and usage of derived datatypes, matching their type signatures in communication, and detecting erroneous overlaps of communication buffers. We implement these checks in the MUST runtime error detection framework. We provide a novel representation of error locations to highlight usage errors. Further, approaches to buffer overlap checking can cause unacceptable overheads for non-contiguous datatypes. We present an algorithm that uses patterns in derived MPI datatypes to avoid these overheads without losing precision. Application results for the benchmark suites SPEC MPI2007 and NAS Parallel Benchmarks for up to 2048 cores show that our approach applies to a broad range of applications and that our extended overlap check improves performance by two orders of magnitude. Finally, we augment our runtime error detection component with a debugger extension to support in-depth analysis of the errors that we find as well as semantic errors. This extension to gdb provides information about MPI datatype handles and enables gdb - and other debuggers based on gdb - to display the content of a buffer as used in MPI communications.

关键词： MPI datatypes runtime error detection debugging

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A Secure and Hierarchical architecture for P2PSIP Session Initiation

A Secure and Hierarchical Architecture for P2PSIP Session In...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Zheng, Xianghan Guo, Wenzhong Zhong, Shangping Yu, Zhiyong Fuzhou Univ Coll Math & Comp Sci Fuzhou 350108 Peoples R China Fuzhou Univ Fujian Key Lab Sci & Engn Comp Fuzhou 350108 Peoples R China

ISBN: (纸本)9780769546766

Recently, both academia and industry have initiated research projects directed on integration of P2PSIP paradigm into communication systems. In this paradigm, P2P network stores most of the network information among participating peers without help of the central servers. The concept of self-configuration, self-establishment greatly improves the robustness of the network system compared with the traditional Client/Server based systems. In this paper, we propose a system architecture for constructing secure P2PSIP session initiation. The proposed approaches include: three-layer hierarchical overlay division, proxy based security, subjective logic based trust enhancement, NAT traversal, message routing, etc. After that, a prototype with 512 P2PSIP peers is implemented. We evaluate the system architecture in several aspects: implementation testing, Number of hops and the protection against malicious or compromised intermediate peers. We take Chord as the P2PSIP overlay asexample. However, this system architecture is independent of Chord overlay and could be extended to the other DHT (Distributed Hash Table) technologies.

关键词： Peer-to-Peer (PCP) Session Initiation Protocol (SIP) P2PSIP Chord Chord Secure Proxy (CSP) Chord Secure Proxy Gateway (CSPG) Subjective logic

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Modeling for Synthesis with System#

Modeling for Synthesis with System#

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Koellner, C. Mendoza, F. Mueller-Glaser, K. D. FZI Res Ctr Informat Technol Dept Embedded Syst & Sensors Engn ESS Haid & Neu Str 10-14 D-76131 Karlsruhe Germany Karlsruhe Inst Technol Inst Informat Proc Technol D-76021 Karlsruhe Germany

ISBN: (纸本)9780769546766

While Electronic Design Automation made the shift towards system design and high-level design methods keep on emerging, there is hardly any open framework which allows researchers to quickly prototype novel synthesis algorithms. We present System#, an open source system level design framework based on C#. System# tries to bridge the productivity gap by covering modeling, simulation, code transformations and VHDL code generation in a single extensible platform. We explain how common modeling principles, such as component-based design, the separation of communication and computation, concurrent behavior and time are realized in System#. The implementation of an appropriate simulator kernel is discussed. We demonstrate the potential of code transformations by giving application examples: converting a cycle-accurate sequential specification to an explicit synthesizable finite state machine representation and IP-based design. We conclude that System# is an appropriate research and integration platform which has the potential to add value to the research community.

关键词： System-level design Reconfigurable logic Csharp Dotnet Systemsharp Design automation Very high speed integrated circuits

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Surface wave communication system for on-chip and off-chip interconnects

Surface wave communication system for on-chip and off-chip i...

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5th International workshop on Network on Chip architectures, NoCArc 2012, Held in Conjunction with the 45th Annual ieee/ACM International Symposium on Microarchitecture, MICRO 2012

作者： Karkar, Ammar Al-Dujaily, Ra'ed Yakovlev, Alex Tong, Kenneth Mak, Terrence School of Electrical and Electronic Engineering Newcastle University Newcastle upon Tyne United Kingdom Department of Electrical and Electronic Engineering University College London United Kingdom Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong Hong Kong University of Kufa Najaf-Iraq Iraq

ISBN: (纸本)9781450315401

Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal based interconnect pursuit offers limited scalability with the relentless technology scaling. To meet the scalability demand, this paper proposes a new hybrid interconnect fabric empowered by metal interconnect NoC and Zenneck surface Waves Interconnect (SWI) technology. Our initial results show a considerable power reduction (9 to 17%) and performance improvement (35%) of the proposed hybrid architecture compared to regular NoC. These results are achieved over relatively small hardware and area overhead (2.29% of die). This paper explores promising potentials of SWI for future System-on-Chip (SoC) global communication. Copyright 2012 ACM.

关键词： Network-on-chip

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Hybrid static/dynamic scheduling for already optimized dense matrix factorization

Hybrid static/dynamic scheduling for already optimized dense...

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26th ieee International Parallel and Distributed Processing Symposium (IPDPS) / workshop on high performance Data Intensive Computing

作者： Donfack, Simplice Grigori, Laura Gropp, William D. Kale, Vivek Univ Paris 11 INRIA Saclay Ile France Bat 425 F-91405 Orsay France Univ Illinois Dept Comp Sci Urbana IL 61801 USA

ISBN: (纸本)9780769546759

We present the use of a hybrid static/dynamic scheduling strategy of the task dependency graph for direct methods used in dense numerical linear algebra. This strategy provides a balance of data locality, load balance, and low dequeue overhead. We show that the usage of this scheduling in communication avoiding dense factorization leads to significant performance gains. On a 48 core AMD Opteron NUMA machine, our experiments show that we can achieve up to 64% improvement over a version of CALU that uses fully dynamic scheduling, and up to 30% improvement over the version of CALU that uses fully static scheduling. On a 16-core Intel Xeon machine, our hybrid static/dynamic scheduling approach is up to 8% faster than the version of CALU that uses a fully static scheduling or fully dynamic scheduling. Our algorithm leads to speedups over the corresponding routines for computing LU factorization in well known libraries. On the 48 core AMD NUMA machine, our best implementation is up to 110% faster than MKL, while on the 16 core Intel Xeon machine, it is up to 82% faster than MKL. Our approach also shows significant speedups compared with PLASMA on both of these systems.

关键词： dynamic scheduling communication-avoiding LU factorization numerical linear algebra

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Improving performance in a combined router/server

Improving performance in a combined router/server

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ieee workshop on high performance Switching and Routing

作者： Voravit Tanyingyong Markus Hidell Peter Sjödin School of Information and Communication Technology Royal Institute of Technology (KTH) Kista Sweden

A modern PC-based router can provide as competitive service as a specialized hardware router while offering more flexibility and possibility to extend beyond routing. We focus on a use case in which the PC-based router also functions as a server. In this paper, we propose a multi-core based architecture for a combined router/server that efficiently provides simultaneous packet forwarding and server processing. We improve the overall performance by creating a fast path for packet forwarding through caching flow entries in on-board classification hardware on the NIC. We propose a generic design based on multi-core processors and multi-queue network interface cards. We describe a prototype implementation and present an experimental evaluation of this design. We also devise a strategy for how to efficiently map packet forwarding and application processing tasks onto the multi-core architecture.

关键词： Servers Hardware Computer architecture Central Processing Unit Throughput Kernel

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ieee 1451.4 embedded smart sensors architecture for wheelchair user monitoring

IEEE 1451.4 embedded smart sensors architecture for wheelcha...

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ieee International workshop on Medical Measurement and Applications (MEMEA)

作者： Octavian Postolache Pedro Silva Girão Hamza Ijaz João Freire Instituto de Telecomunicaçes ISCTE-IUL Instituto Universitário de Lisboa (ISCTE) Lisboa Portugal Instituto de Telecomunicações DEEC IST UTL Lisboa Portugal Instituto de Telecommunicações Lisboa Portugal School of ICT Royal Institute of Technology Stockholm Sweden

The design and implementation of a microcontroller based platform compatible with ieee 1451.4 standard for high performance unobtrusive accurate cardio-respiratory and motor activity estimation of wheelchair users are presented in this paper. The platform is a multi-sensor architecture that includes sensors with plug-and-play and auto-identification capabilities, a RFID reader that is used to identify the wheelchair user, and RFID tags mounted in critical regions of the indoor habitat. The acquired data from the smart sensor channels are delivered through Bluetooth communication or wired serial communication to a host computer that includes a server application associated with ieee 1451.4 TEDS management and display of the measured data. Elements of human-machine-interface (HMI) implementation and several experimental results are included in the paper.

关键词： Intelligent sensors Wheelchairs Microcontrollers Biosensors Standards Transducers

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G-COPSS: A Content Centric communication Infrastructure for Gaming Applications

G-COPSS: A Content Centric Communication Infrastructure for ...

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18th ieee workshop on Local and Metropolitan Area Networks (LANMAN)

作者： Chen, Jiachen Arumaithurai, Mayutan Fu, Xiaoming Ramakrishnan, K. K. Univ Goettingen Inst Comp Sci Gottingen Germany NFC Lab Europe Heidelberg Germany AT&T Labs Res Florham Pk NJ USA

ISBN: (纸本)9781457712654

With users increasingly focused on an online world, an emerging challenge for the network infrastructure is the need to support Massively Multiplayer Online Role Playing Games (MMORPG). This is an application domain that is attracting more players than ever before, very often with players distributed over a metropolitan area. Currently, MMORPG are built on an IP infrastructure with the primary responsibility on servers to do the work of disseminating control messages and having to predict/retrieve objects in each player's view. Limited server resources significantly impair the user's interactive experience. Modern fast-paced action games that run on a client/server architecture limit the number of players who can interact simultaneously since the server needs to handle the frequent updates and disseminate them. Scale and timeliness are major challenges of such a server-oriented gaming architecture. We propose Gaming over COPSS (G-COPSS), a communication infrastructure using a Content-Oriented Pub/Sub System (COPSS) to enable efficient decentralized information dissemination in MMORPG, exploiting the network and the end-systems for player management and information dissemination. We emulate an application that is particularly emblematic of MMORPG - Counter-Strike - but one in which all the players share a hierarchical structured map. Using trace-driven simulation, we demonstrate that G-COPSS can achieve high scalability and tight timeliness requirements of MMORPG. The simulator is parameterized using the results of careful microbenchmarking of the open-source CCN implementation and of standard IP-based forwarding. Our evaluations show that G-COPSS provides considerable performance improvement in terms of aggregate network load and update latency compared to that of a traditional IP server-based infrastructure.

关键词： Aggregates Engines G-COPSS communication infrastructure Games IP networks IP networks IP server-based infrastructure MMORPG Network topology Servers Subscriptions client-server architecture client-server systems computer games content centric communicatio

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