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2011 ieee Swedish communication Technologies workshop, Swe-CTW 2011

2011 IEEE Swedish Communication Technologies Workshop, Swe-C...

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2011 ieee Swedish communication Technologies workshop, Swe-CTW 2011

ISBN: (纸本)9781457718786

The proceedings contain 23 papers. The topics discussed include: high-speed single-frequency network for HSDPA;investigation of spectrally efficient transmission for differently modulated optical signals in mixed data rates WDM systems;performance study of node placement for geographic routing in WSNs;nonlinear distributed sensing for closed-loop control over Gaussian channels;capacity of the channel with action-dependent state and reversible input;extending the reach of DWDM-PON access network using chromatic dispersion compensation;implementation of LTE SC-FDMA on the USRP2 software defined radio platform;uplink performance analysis of multicell MU-MIMO with zero-forcing receivers and perfect CSI;a constrained optimization approach to nonlinear interference cancellation;nonlinear transmission strategies for a general half-duplex AWGN relay channel;an all-photonic digital radio over fiber architecture;and performance analysis of space-time block codes over generalized-K fading MIMO channels.

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implementation and verification of autonomous decentralized flow control based on local interaction

Implementation and verification of autonomous decentralized ...

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International workshop on Assurance in Distributed Systems and Networks

作者： Sumi, Tatsuro Takano, Chisa Ishida, Kenji Aida, Masaki Graduate School of System Design Hiroshima City University 3-4-1 Ozuka-Higashi Asa-Minami-Ku Hiroshima 731-3194 Japan Graduate School of System Design Tokyo Metropolitan University Hino-shi Tokyo 191-0065 Japan

ISBN: (纸本)9780769543499

We have already proposed the framework of autonomous decentralized control based on local-interaction as a novel control mechanism for communication networks. This framework is based on the relation between local interaction and the solution yielded by a partial differential equation. In this framework, the state of the complete system is controlled by appropriately designing the autonomous operation of the subsystems. That is, the local action rules (micro-level) are designed to produce an appropriate state of the whole system at the macro-level. Our previous studies proposed diffusion-type flow control (DFC) as a solution for the extremely time-sensitive flow control required by high-speed networks and we have evaluated the performance of DFC by simulation. In this paper, to apply DFC to real networks, we show the technique to implement the DFC functions on PCs and to investigate its performance in the presence of TCP.

关键词： Flow control

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VLSI architecture for soft-output tuple search sphere decoding

VLSI architecture for soft-output tuple search sphere decodi...

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ieee workshop on Signal Processing Systems (SIPS)

作者： Esther P. Adeva M. Ali Shah Björn Mennenga Gerhard Fettweis Vodafone Chair Mobile Communication Systems Technische Universität Dresden Dresden Germany

high detection complexity is known to be one of the major challenges in MIMO communications based on spatial multiplexing. Tuple Search Detector (TSD) was recently introduced, significantly reducing detection complexity in comparison to conventional algorithms while achieving close to full max-log-APP BER performance. Irregular control flow and sequential nature of depth-first-based detectors frustrate efficient application of parallelization techniques, typically leading to inefficient realizations. This work presents a novel TSD implementation, based on a scalable and parallelizable pipelined ASIP architecture. The proposed VLSI design is implemented for 4×4 MIMO transmission using 64-QAM constellation on 65-nm CMOS technology. In low SNR scenarios, proposed detector achieves 403.6 Mbps throughput at 454 MHz clock frequency. TSD can be moreover adjusted according to transmission conditions, reaching >;1 Gbps. A silicon area of 0.14 mm 2 (98.9 kGEs) is occupied by the TSD core, reporting low power dissipation (57.94 mW) under typical case operating conditions. Proposed detector implementation achieves close to full max-log-APP BER performance and high detection throughput with reasonable hardware complexity, by far outperforming state-of-the-art realizations.

关键词： Detectors Throughput Measurement MIMO Complexity theory Bit error rate Computer architecture

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G-COPSS: A content centric communication infrastructure for gaming applications

G-COPSS: A content centric communication infrastructure for ...

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ieee workshop on Local and Metropolitan Area Networks (LANMAN)

作者： Jiachen Chen Mayutan Arumaithurai Xiaoming Fu K. K. Ramakrishnan Institute of Computer Science University of Goettingen Germany AT&T Laboratories Research Florham Park NJ USA

With users increasingly focused on an online world, an emerging challenge for the network infrastructure is the need to support Massively Multiplayer Online Role Playing Games (MMORPG). This is an application domain that is attracting more players than ever before, very often with players distributed over a metropolitan area. Currently, MMORPG are built on an IP infrastructure with the primary responsibility on servers to do the work of disseminating control messages and having to predict/retrieve objects in each player's view. Limited server resources significantly impair the user's interactive experience. Modern fast-paced action games that run on a client/server architecture limit the number of players who can interact simultaneously since the server needs to handle the frequent updates and disseminate them. Scale and timeliness are major challenges of such a server-oriented gaming architecture. We propose Gaming over COPSS (G-COPSS), a communication infrastructure using a Content-Oriented Pub/Sub System (COPSS) to enable efficient decentralized information dissemination in MMORPG, exploiting the network and the end-systems for player management and information dissemination. We emulate an application that is particularly emblematic of MMORPG - Counter-Strike - but one in which all the players share a hierarchical structured map. Using trace-driven simulation, we demonstrate that G-COPSS can achieve high scalability and tight timeliness requirements of MMORPG. The simulator is parameterized using the results of careful microbenchmarking of the open-source CCN implementation and of standard IP-based forwarding. Our evaluations show that G-COPSS provides considerable performance improvement in terms of aggregate network load and update latency compared to that of a traditional IP server-based infrastructure.

关键词： Servers Games IP networks Subscriptions Network topology Aggregates Engines

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100GB/S two-iteration concatenated BCH decoder architecture for optical communications

100GB/S two-iteration concatenated BCH decoder architecture ...

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workshop on Signal Processing Systems

作者： Lee, Kihoon Kang, Han-Gil Park, Jeong-In Lee, Hanho School of Information and Communication Engineering Inha University Incheon 402-751 Korea Republic of

ISBN: (纸本)9781424489336

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. The proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10-15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications. ©2010 ieee.

关键词： Concatenated codes

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Three high performance architectures in the parallel APMC boat

Three high performance architectures in the parallel APMC bo...

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9th International workshop on Parallel and Distributed Methods in Verification, PDMC 2010 - Joint with the 2nd International workshop on high-performance Computational Systems Biology, HiBi 2010

作者： Hamidouche, Khaled Borghi, Alexandre Esterie, Pierre Falcou, Joel Peyronnet, Sylvain LRI CNRS Univ. Paris-Sud 91405 Orsay France

ISBN: (纸本)9780769542652

Approximate probabilistic model checking, and more generally sampling based model checking methods, proceed by drawing independent executions of a given model and by checking a temporal formula on these executions. In theory, these methods can be easily massively parallelized, but in practice one has to consider, for this purpose, important aspects such as the communication paradigm, the physical architecture of the machine, etc. Moreover, being able to develop multiple implementations of this algorithm on architectures as different as a cluster or many-cores requires various levels of expertise that may be problematic to gather. In this paper we propose to investigate the runtime behavior of approximate probabilistic model checking on various state of the art parallel machines - clusters, SMP, hybrid SMP clusters and the Cell processor - using a high-level parallel programming tool based on the Bulk Synchronous Parallelism paradigm to quickly instantiate model checking problems over a large variety of parallel architectures. Our conclusion assesses the relative efficiency of these architectures with respect to the algorithm classes and promotes guidelines for further work on parallel APMC implementation. © 2010 ieee.

关键词： Parallel programming

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Verification of the CoreNet fabric with SystemVerilog

Verification of the CoreNet fabric with SystemVerilog

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10th International workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009

作者： Page IV, Robert C. Jain, Sakar Power Cores and Platforms NMG Freescale Semiconductor Inc. Austin TX United States

ISBN: (纸本)9780769540009

The Freescale QorIQ™ communication platforms are system-on-chip (SoC) processors containing single, dual and many cores and enable the next era of networking by offering advanced levels of performance, power-efficiency and programmability. The QorIQ P4080 communications processor, the signature member of the product line, integrates eight enhanced Freescale Power architecture® processors, a tri-level cache hierarchy, and innovative high-speed CoreNet™ fabric and data path acceleration. The CoreNet fabric is an interconnect architecture suitable for scalable on-chip network to connect multiple Power architecture processing cores with caches, stand-alone caches and memory subsystems. The CoreNet fabric was designed to provide a coherent multicore migration solution enabling the move to multicore. This paper focuses on the verification challenges and solutions associated with verifying the CoreNet platform using SystemVerilog (SV). © 2009 ieee.

关键词： Memory architecture

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A high-performance capabilities-based network protocol

A high-performance capabilities-based network protocol

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ieee workshop on Secure Network Protocols (NPSec)

作者： Tilman Wolf Kamlesh T. Vasudevan Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Capabilities-based networks present a fundamental shift in the security design of network architectures. Instead of permitting the transmission of packets from any source to any destination, routers deny forwarding by default. For a successful transmission, packets need to positively identify themselves and their permissions to the router. A major challenge for a high-performance implementation of such a network is an efficient design of the credentials that are carried in the packet and the verification procedure on the router. Based on our prior work on the design of packet credentials, we present a network protocol that implements these concepts. Our prototype implementation shows that there is some connection setup cost associated with this type of secure communication. However, once a connection is established, the throughput performance of a capabilities-based connection is similar to that of conventional TCP.

关键词： Protocols Telecommunication traffic communication system traffic control Internet Computer crime Prototypes Authentication Computer architecture Throughput Access control

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Real-time FPGA implementation of Lorenz's chaotic generator for ciphering telecommunications

Real-time FPGA implementation of Lorenz's chaotic generator ...

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Annual ieee Northeast workshop on Circuits and Systems (NEWCAS)

作者： M. S. Azzaz C. Tanougast S. Sadoudi A. Dandache Laboratoire Systemes de Communications Ecole Militaire Polytechnique Alger Algerie Laboratoire LICM Université Paul Verlaine de Metz Metz France

In this paper, we present a new approach for realtime FPGA implementation of the random key based Lorenz's chaotic generator for data stream encryption. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and presented using Virtex Xilinx FPGA. This architecture employs only 1926 slices and allows achieving a random key throughput rate of 124 Mbps by using a low system clock with a frequency of up to 15,5 MHz allowing low power consumption especially for embedded applications.

关键词： Field programmable gate arrays Chaos Chaotic communication Cryptography Hardware Frequency synchronization Transmitters Data security Throughput CMOS technology

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A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

A novel architecture for a high-performance network processi...

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ieee workshop on high performance Switching and Routing

作者： Simon Hauger Institute of Communication Networks and Computer Engineering (IKR) Universität Stuttgart Stuttgart Germany

Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at register transfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based high speed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with today's field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.

关键词： Field programmable gate arrays Computer architecture Prototypes Throughput Pipelines high-speed networks Protocols Ethernet networks communication networks Computer networks

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