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From Local to Remote: Scaling VisIVO Visual Analytics for Large-Scale Astrophysical Data Visualization

From Local to Remote: Scaling VisIVO Visual Analytics for La...

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Euromicro conference on parallel, Distributed and network-Based Processing

作者： Giuseppe Tudisco Fabio Vitello Eva Sciacca Ugo Becciani Osservatorio Astrofisico di Catania Istituto Nazionale di Astrofisica (INAF) Catania Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

As the Square Kilometre Array (SKA) radio telescopes approach full operation, they are set to generate hundreds of petabytes of data annually, offering unprecedented resolution and detail in astrophysical observations. This massive influx of data presents significant challenges in terms of storage, processing, analysis and visualization. Scientific visualization becomes essential in this context, enabling researchers to interpret complex, high-dimensional datasets and extract valuable insights. This paper presents the latest developments of VisIVO Visual Analytics, an interactive visualization tool that is evolving to meet the needs of the SKA and similar large-scale astrophysical projects such as the James Webb Space Telescope and the Atacama Large Millimeter/submillimeter Array (ALMA). Originally designed as a desktop application, VisIVO is transitioning to a client-server architecture, allowing it to efficiently run remote visualization pipelines on remote servers. This shift significantly enhances the tool’s ability to handle large scale datasets, facilitating real-time, interactive analysis of complex data. This work also explores how VisIVO Visual Analytics can distribute computational workloads across multiple nodes in high-performance computing (HPC) clusters for parallel visualization pipelines, enabling advanced and interactive techniques to derive meaningful insights from the vast volumes of data generated by next-generation observatories.

关键词： Radio astronomy Visual analytics High performance computing Pipelines Data visualization Computer architecture Telescopes Arrays Servers Usability

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Execution Time Optimization for Pipeline Deep network Training on Multiple GPUs

Execution Time Optimization for Pipeline Deep Network Traini...

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Euromicro conference on parallel, Distributed and network-Based Processing

作者： Bing-Jou Wu Ding-Yong Hong Pangfeng Liu Jan-Jan Wu Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan Institute of Information Science Academia Sinica Taipei Taiwan

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

As neural network models become gigantic, they increasingly demand more time and memory for training. To meet these demands, advanced parallel computing techniques have become essential. Our research focuses on hybrid parallelism, an extension of pipeline parallelism. Pipeline parallelism splits the neural network into sub-networks distributed across a sequence of processing units, enabling simultaneous processing of different data segments on each device. Hybrid parallelism extends this concept by allocating multiple devices to each sub-network. Our research focuses on optimizing hybrid parallelism by improving how the model is partitioned and how computational devices are assigned. We address these issues by modeling the neural network as a directed acyclic graph of tensor operators, and then demonstrating that optimally partitioning this graph is NP-complete. Then, we propose a two-step approach. The first step is to determine a sequence of nodes. The second step is dynamic programming, which partitions the sequence to maintain balance across the assigned devices. In transforming the graph into a sequence, we explore two methods: one employs topological sorting, while the other clusters non-sequential subgraphs. We apply both methods and select the more effective one based on performance outcomes. We implement our algorithm and conduct experiments. The results show substantial enhancements in both the speed of partitioning and training throughput, with speedups reaching up to 23 in partitioning time and a 1.3 -fold increase in training throughput.

关键词： Training Directed acyclic graph Computational modeling Neural networks Pipelines Computer architecture parallel processing Throughput Dynamic programming Topology

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Topology Decoupled All-reduce Algorithm

Topology Decoupled All-reduce Algorithm

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Ruixing Zong Jiapeng Zhang Zhuo Tang Anwitaman Datta College of Computer Science and Electronic Engineering Hunan University China College of Computing and Data Science Nanyang Technological University Singapore Faculty of Computing Engineering and Media De Montfort University Leicester United Kingdom

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

With the advancement of deep learning, network communication has become the most critical factor in model training. Especially, the all-reduce operation can comprise over 70% of the cumulative training duration as a pivotal component within data parallelism. However, existing all-reduce algorithms often perform poorly in complex network topologies, and there is currently no universal and straightforward all-reduce algorithm that can effectively adapt to diverse topological *** this work, we propose a topology decoupled all-reduce algorithm. We decouple the network into multiple tree substructures, select the trees with the smallest heights, and then split the data to perform aggregate communication within these selected structures. This approach significantly reduces the number of communications and enhances efficiency. Experimental results show that our topology decoupled all-reduce algorithm reduces communication time compared to NCCL’s by 42.9% and enhances end-to-end training efficiency by 11.7%.

关键词： Training Deep learning Adaptation models Signal processing algorithms Complex networks Signal processing parallel processing Data aggregation Topology Speech processing

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Modeling and Simulation of Collective Algorithms on HPC network Topologies using Structural Simulation Toolkit 24

Modeling and Simulation of Collective Algorithms on HPC Netw...

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Proceedings of the SC '24 Workshops of the international conference on High Performance computing, network, Storage, and Analysis

作者： Sai P. Chenna Michael Steyer Nalini Kumar Maria Garzaran Philippe Thierry Intel Corporation

ISBN: (纸本)9798350355543

In the last decade, DL training has emerged as an HPC-scale workload running on large clusters, the size of the largest supercomputers on the Top500 list. The dominant communication pattern in distributed data-parallel DL training is allreduce which is used to sum the model gradients across processes during backpropagation phase. Various allreduce algorithms have been developed to optimize communication time in DL training. Given the scale of DL workloads, it is crucial to evaluate the scaling efficiency of these algorithms on a variety of system architectures. We have extended the Structural Simulation Toolkit (SST) to simulate allreduce and barrier algorithms -Rabenseifner, ring, and, dissemination algorithms. We performed a design space exploration (DSE) study with three allreduce algorithms and two barrier algorithms running on six system network topologies for various message sizes. We quantified the performance benefits of using allreduce algorithms which preserve locality between communicating processes. In addition, we evaluated the scaling efficiency of centralized and decentralized barrier algorithms.

关键词： collectives

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BrahMap: A scalable and modular map-making framework for the CMB experiments

BrahMap: A scalable and modular map-making framework for the...

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Euromicro conference on parallel, Distributed and network-Based Processing

作者： Avinash Anand Giuseppe Puglisi Dipartimento di Fisica Università di Roma Tor Vergata Via della Ricerca Scientifica 1 Roma Italy INFN Sezione di Roma2 Università di Roma Tor Vergata Via della Ricerca Scientifica 1 Roma Italy Dipartimento di Fisica e Astronomia Università degli Studi di Catania Via S. Sofia 64 Catania Italy INAF Osservatorio Astrofisico di Catania Via S.Sofia 78 Catania Italy INFN Sezione di Catania Via S.Sofia 64 Catania Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The cosmic microwave background (CMB) experiments have reached an era of unprecedented precision and complexity. Aiming to detect the primordial B-mode polarization signal, these experiments will soon be equipped with $10^{4}$ to $10^{5}$ detectors. Consequently, future CMB missions will face the substantial challenge of efficiently processing vast amounts of raw data to produce the initial scientific outputs - the sky maps - within a reasonable time frame and with available computational resources. To address this, we introduce BrahMap, a new map-making framework that will be scalable across both CPU and GPU platforms. Implemented in C++ with a user-friendly Python interface for handling sparse linear systems, BrahMap employs advanced numerical analysis and high-performance computing techniques to maximize the use of super-computing infrastructure. This work features an overview of the BrahMap’s capabilities and preliminary performance scaling results, with application to a generic CMB polarization experiment.

关键词： Numerical analysis Scalability Object oriented modeling Pipelines Graphics processing units Numerical models parallel algorithms Object oriented programming Physics Python

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Optimizing MILC-Dslash Performance on NVIDIA A100 GPU: parallel Strategies using SYCL 24

Optimizing MILC-Dslash Performance on NVIDIA A100 GPU: Paral...

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Proceedings of the SC '24 Workshops of the international conference on High Performance computing, network, Storage, and Analysis

作者： Amanda S. Dufek Steven A. Gottlieb Muaaz Gul Awan Douglas Adriano Augusto Jack Deslippe Brandon Cook NERSC Lawrence Berkeley National Lab Berkeley CA USA Department of Physics Indiana University Bloomington IN USA Oswaldo Cruz Foundation Rio de Janeiro RJ Brazil

ISBN: (纸本)9798350355543

MILC-Dslash is a benchmark that is derived from the MILC code which simulates lattice-gauge theory on a four-dimensional hypercube. This paper outlines a gradual progression in increasing the granularity of parallelism in the MILC-Dslash kernel using the SYCL programming model, transitioning from a simple to a fully parallel implementation. We explore the impact of various parallel strategies on the MILC-Dslash performance on an NVIDIA A100 GPU. This investigation encompasses different work-item index orders, work-group sizes, and memory access patterns that arise from these strategies. Examples of components intertwined with the parallel strategies include atomic memory operations, shared variables, divergent instructions, synchronization barrier, scenarios with and without dependencies between iterations, as well as versions with and without using the SYCL complex library (SyclCPLX) and the SYCLomatic tool. The best parallel strategy is twice as fast as the simplest strategy and shows a 10% improvement over the QUDA baseline, thanks to enhanced parallelism and the use of work-group local memory. This, along with other findings --- such as optimizing GPU resource utilization even at the expense of concurrency, prioritizing the use of work-item indexing methods that favor more localized memory access patterns, and maximizing both the number of active work-items per warp and the sequence of successive active work-items --- could provide valuable guidance for researchers and developers seeking to optimize parallel computing applications.

关键词： MILC-Dslash

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Fast and Energy-Efficient N-Body Simulation on FPGA through High-Level Synthesis

Fast and Energy-Efficient N-Body Simulation on FPGA through ...

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Euromicro conference on parallel, Distributed and network-Based Processing

作者： Paolo Palazzari Marco Faltelli Francesco Iannone Francesco Pascarella ENEA Lungotevere Thaon di Revel 76 Rome Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The N -body problem is a classical computational challenge that involves integrating the motion equations of a system of interacting bodies. This problem is computationally demanding and, as power consumption becomes a critical issue in computing systems, increasing the energy efficiency of solutions is essential. To address this, we use FPGA accelerators to implement the acceleration computation, the most demanding part of the integration algorithm. FPGAs are known for their low power requirements and high internal parallelism, but they traditionally require hardware programming skills. With High-Level Synthesis (HLS) now well established, we leverage the AMD Vitis HLS toolchain to implement the acceleration computation for the N-body problem. After analyzing the various forms of parallelism at different levels of granularity in the acceleration computation, we design a parallel architecture, implemented on an FPGA using the HLS flow. The speed and energy efficiency of our solution are compared against high-end CPU implementations, showing substantial improvements. Our FPGA implementation achieves 30.4 GPair/s and $697\ \mathrm{MPair} / \mathrm{s} / \mathrm{W}$, significantly outperforming previous FPGA and CPU solutions in both speed and power consumption.

关键词： Power demand Multicore processing parallel processing Programming Energy efficiency Mathematical models Hardware Computational efficiency Field programmable gate arrays

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Analysis of Time Synchronization Challenges in Digital Twins for Edge-Enabled Data Centers in Smart Cities Scenario

Analysis of Time Synchronization Challenges in Digital Twins...

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Euromicro conference on parallel, Distributed and network-Based Processing

作者： Stefano Rinaldi Salvatore Dello Iacono Paolo Bellagente Marco Pasetti Department of Information Engineering University of Brescia Brescia Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The rapid adoption of Internet of Things (IoT) technologies and digital twins (DTs) is revolutionizing smart cities by facilitating improved real-time monitoring, simulation, and optimization of urban infrastructures. In data centers, digital twins offer virtual representations of physical infrastructure, enabling real-time monitoring, optimization of energy consumption, cooling efficacy, and resource utilization. This integration seeks to improve energy efficiency and sustainability in smart cities. In this context, edge computing is becoming essential solutions to mitigate latency, bandwidth, and privacy issues linked to centralized cloud system. A significant challenge in utilizing digital twins for edge-enabled data centers is attaining accurate time synchronization between the digital twin and its physical equivalent. Precise synchronization is crucial for real-time state representation, facilitating efficient monitoring, control, and optimization. The distributed characteristics of edge devices, varying network conditions, and constrained computational resources present considerable synchronization challenges. Factors such as clock drift, network jitter, and protocol constraints can result in temporal inconsistencies, compromising the reliability of digital twin applications. This paper offers an extensive examination of time synchronization issues in digital twins for edge-enabled data centers within smart city contexts. The study examines essential factors affecting synchronization accuracy and reliability, identifies significant bottlenecks, and suggests strategies to alleviate their impact. The results aid in the creation of effective synchronization mechanisms, facilitating the implementation of dependable digital twin systems.

关键词： Data centers Protocols Smart cities Real-time systems Digital twins Synchronization Reliability Sustainable development Optimization Edge computing

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Attack Graph Generation on HPC Clusters 30th

Attack Graph Generation on HPC Clusters

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30th international conference on parallel and Distributed Processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied computing, CSCE 2024

作者： Li, Ming Hale, John The University of Tulsa TulsaOK74104 United States

ISBN: (纸本)9783031856372

Attack graphs (AGs) are graphical tools to analyze the security of computer networks. By connecting the exploitation of individual vulnerabilities, AGs expose possible multi-step attacks against target networks, allowing system administrators to take preventive measures to enhance their network’s security. As powerful analytical tools, however, AGs are both time- and memory-consuming to be generated. As the numbers of network assets, interconnections between devices, as well as vulnerabilities increase, the size and volume of the resulting AGs grow at a much higher rate, leading to the well-known state-space explosion. In this paper, we propose the use of high performance computing (HPC) clusters to implement AG generators. We evaluate the performance through experiments and provide insights into how cluster environments can help resolve the issues of slow speed and high memory demands in AG generation in a balanced way. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Attack Graph Cybersecurity High Performance computing

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ActorProf: A Framework for Profiling and Visualizing Fine-grained Asynchronous Bulk Synchronous parallel Execution 24

ActorProf: A Framework for Profiling and Visualizing Fine-gr...

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Proceedings of the SC '24 Workshops of the international conference on High Performance computing, network, Storage, and Analysis

作者： Jiawei Yang Shubhendra Pal Singhal Jun Shirako Akihiro Hayashi Vivek Sarkar Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9798350355543

A Fine-grained Asynchronous Bulk Synchronous parallel (FA-BSP) model is an extended version of the existing BSP model that facilitates fine-grained asynchronous point-to-point messages with automatic message aggregation. While many large irregular applications written with the FA-BSP model demonstrate promising performance, no profiler is aware of profile-worthy portions of an FA-BSP program and visualizes the results in an intuitive way. This is reasonable because the FA-BSP program relies on multiple external libraries, and the runtime frequently switches between different portions of the program, which makes it difficult for well-established profilers like score-p, TAU(τ), CrayPat, Intel®Vtune™, and HPCToolkit to profile and visualize these portions in an FA-BSP-friendly *** paper designs and implements a profiling and visualization framework called ActorProf. The framework enables 1) asynchronous point-to-point message-aware profiling with hardware performance counters, 2) overall performance breakdown that is aware of FA-BSP execution, and 3) visualization of these profiling results.

关键词： ActorProf

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