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Design of (2, 1, N) parallel Convolutional encodes for VLSI

Design of (2, 1, N) Parallel Convolutional encodes for VLSI

引用

international conference on Mechatronics and Industrial Informatics (ICMII 2013)

作者： Duan, Maoqiang Huang, Xiaoli Chinese Acad Sci Lab Ind Control Network & Syst Shenyang Inst Automat Shenyang Liaoning Peoples R China Inst Sci & Tech Informat Liaoning Prov Competit Intelligence Ctr Shenyang Liaoning Peoples R China

ISBN: (纸本)9783037856949

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35 mu m CMOS technology;hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

关键词： convolutional encodes parallel computing low power dissipation

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Interconnection networks with Efficient Custom Routing, Exploiting Small-World Effect

Interconnection Networks with Efficient Custom Routing, Expl...

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IEEE RIVF international conference on computing and Communication Technologies - Research, Innovation, and Vision for the Future (RIVF)

作者： Le, Nhat T. X. Nguyen, Van K. Ha Noi Univ Sci & Technol Hanoi Vietnam

ISBN: (纸本)9781479913497;9781479913503

We design a new interconnection network topology and a custom routing algorithm, which targets solving new challenging issues posed by recent advanced studies in the areas of massively parallel computing and large-scale data centers. We follow the design principles of Distributed Shortcut networks (DSN) [1], which construct non-random topologies with the creation of long-range Shortcuts inspired by observations in small-world networks. As a result, our new DSN-alpha networks performs significantly better than the basic DSN in term of communication latency while provide an surprisingly load balance which helps the network become robust against burst of traffic demand while topology-agnostic deadlock-free routing (e.g. the up*/down*) suffers a lot.

关键词： network topologies small-world networks interconnection networks high-performance computing

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Load Balancing and parallel Computation Model for Performance and Accuracy over the Cluster of Nodes 2

Load Balancing and Parallel Computation Model for Performanc...

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2nd international conference on Innovative Practices in Technology and Management, ICIPTM 2022

作者： Vasuda, V. Srividya, K. Anusha, M. Vasavi College Of Engineering Hyderabad Telangana India

ISBN: (纸本)9781665466431

Cloud computing can be online based network engineering which contributed with a rapid advancement at the progress of communication technological innovation by supplying assistance to clients of assorted conditions with aid from online computing sources. It's terms of hardware and software apps together side software growth testing and platforms applications because tools. Large-scale heterogeneous distributed computing surroundings give the assurance of usage of a huge quantity of computing tools in a comparatively low price. As a way to lessen the software development and setup onto such complicated surroundings, high speed parallel programming languages exist which have to be encouraged by complex operating techniques. There are numerous advantages for consumers in terms of cost and flexibility that come with Cloud computing's anticipated uptake. Building on well-established research in Internet solutions, networks and utility computing, virtualization et cetera Service-Oriented Architectures and the Internet of Services (IoS) have implications for a wide range of technological issues such as parallel computing and load balancing as well as high availability and scalability. Effective load balancing methods are essential to solving these issues. Since such systems' size and complexity make it impossible to concentrate job execution on a few select servers, a parallel distributed solution is required. Adaptive task load model is the name of the method wesuggest in our article for balancing the workload (ATLM). We developed an adaptive parallel distributed computing paradigm as a result of this (ADPM). While still maintaining the model's integrity, ADPM employs a more flexible synchronization approach to cut down on the amount of time synchronous operations use. As well as the ATLM load balancing technique, which solves the straggler issue caused by the performance disparity between nodes, ADPM also applies it to ensure model correctness. The results indicate that

关键词： Application programs

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ReSLB: Load Balanced Workflow for Distributed Deep Learning Mass Spectrometry Database 24

ReSLB: Load Balanced Workflow for Distributed Deep Learning ...

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24th IEEE international conference on High Performance computing and Communications, 8th IEEE international conference on Data Science and Systems, 20th IEEE international conference on Smart City and 8th IEEE international conference on Dependability in Sensor, Cloud and Big Data Systems and Application, HPCC/DSS/SmartCity/DependSys 2022

作者： Mocheng, Li Yang, Liu Yang, Ou Zhiguang, Chen Nong, Xiao Tao, Chen College of Computer National University of Defense Technology Institute for Quantum Information State Key Laboratory of High Performance Computing Changsha China College of Computer National University of Defense Technology Changsha China School of Computer Sun Yat-sen University Guangzhou China Beijing China

ISBN: (纸本)9798350319934

The proteomics data analysis pipeline based on the shotgun method requires efficient data processing methods. The parallel algorithm of mass spectrometry database search faces the problems of rapidly expanding database size but low scalability. The heterogeneous database search algorithm based on deep learning is an effective way to solve this problem. Still, the deep learning-based distributed parallel database search algorithm is lacking. This paper analyzes the database searching computational load using a neural network and designs ReSLB, a workflow for the restricted search of mass spectrometry data based on GPU cluster and neural network scoring algorithm. This work aims to ensure the high scalability of future deep learning-based mass spectrometry distributed databases. In the performance estimation of 256 GPUs, the load imbalance of less than 30% and the parallel efficiency of 60% are achieved. Compared with state-of-the-art, the time cost is reduced by 75%, and the parallel efficiency from 1 to 256 GPUs is 3.6x higher than that. © 2022 IEEE.

关键词： Mass spectrometry

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Low latency communication on DIMMnet-1 network interface plugged into a DIMM slot

Low latency communication on DIMMnet-1 network interface plu...

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international conference on parallel computing in Electrical Engineering (PAR ELEC 2002)

作者： Tanabe, N Hamada, Y Nakajo, H Imashiro, H Yamamoto, J Kudoh, T Amano, H Toshiba Corporation Japan Tokyo University of Agriculture and Technology Japan Hitachi Information Technology Co. Ltd. Japan Hitachi Ltd. Japan National Institute of Advanced Industrial Science and Technology Japan Keio University Japan

ISBN: (纸本)0769517307;0769517315

DIMMnet-1 is a high performance network interface for PC clusters that can be directly plugged into the DIMM slot of a PC. By using both low latency AOTF (Atomic On-The-Fly) sending and high bandwidth BOTF (Block On-The-Fly) sending, it can overcome the overhead caused by standard 110 such as the PCI bus. Two types of DIMMnet-1 prototype boards (providing optical and electrical network interfaces) containing a Martini network interface controller chip are currently available. They can be plugged into a 100MHz DIMM slot of a PC with a Pentium-3, Pentium-4 or Athlon processor. The round-trip time for AOTF on this incompletely tuned DIMMnet-1 is 7.5 times faster than Myrinet2000. The barrier synchronization time for AOTF is 4 times faster than that of an SR8000 supercomputer The inter-two-node floating sum operation time is 1903 ns. This shows that DIMMnet-1 holds promise for applications in which scalable performance with traditional approaches is difficult because of frequent data exchange.

关键词： Agriculture Bandwidth Computer architecture Degradation Delay network interfaces Optical fiber communication Personal communication networks Prototypes Trademarks

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Study and Analysis of Various Task Scheduling Algorithms in the Cloud computing Environment 3

Study and Analysis of Various Task Scheduling Algorithms in ...

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3rd international conference on Advances in computing, Communications and Informatics (ICACCI)

作者： Mathew, Teena Sekaran, K. Chandra Jose, John Rajagiri Sch Engn & Technol Dept Comp Sci & Engn Kochi Kerala India Natl Inst Technol Dept Comp Sci & Engn Surathkal India

ISBN: (纸本)9781479930807

Cloud computing is a novel perspective for large scale distributed computing and parallel processing. It provides computing as a utility service on a pay per use basis. The performance and efficiency of cloud computing services always depends upon the performance of the user tasks submitted to the cloud system. Scheduling of the user tasks plays significant role in improving performance of the cloud services. Task scheduling is one of the main types of scheduling performed. This paper presents a detailed study of various task scheduling methods existing for the cloud environment. A brief analysis of various scheduling parameters considered in these methods is also discussed in this paper.

关键词： Cloud computing Task scheduling Minimum execution time Completion time Cloudsim Energy efficiency Heuristics Makespan

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Performance Analysis and Benchmarking of All-Spin Spiking Neural networks

Performance Analysis and Benchmarking of All-Spin Spiking Ne...

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international Joint conference on Neural networks (IJCNN)

作者： Sengupta, Abhronil Ankit, Aayush Roy, Kaushik Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781509061822

Spiking Neural network based brain-inspired computing paradigms are becoming increasingly popular tools for various cognitive tasks. The sparse event-driven processing capability enabled by such networks can be potentially appealing for implementation of low-power neural computing platforms. However, the parallel and memory-intensive computations involved in such algorithms is in complete contrast to the sequential fetch, decode, execute cycles of conventional von-Neumann processors. Recent proposals have investigated the design of spintronic "in-memory" crossbar based computing architectures driving "spin neurons" that can potentially alleviate the memory-access bottleneck of CMOS based systems and simultaneously offer the prospect of low-power inner product computations. In this article, we perform a rigorous system-level simulation study of such All-Spin Spiking Neural networks on a benchmark suite of 6 recognition problems ranging in network complexity from 10k-7.4M synapses and 195-9.2k neurons. System level simulations indicate that the proposed spintronic architecture can potentially achieve similar to 1292x energy efficiency and similar to 235x speedup on average over the benchmark suite in comparison to an optimized CMOS implementation at 45nm technology node.

关键词： Spiking Neural network Spintronics Domain-Wall Motion All-Spin Crossbar Architectures

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Performance Analysis of Vehicular Delay Tolerant network

Performance Analysis of Vehicular Delay Tolerant Network

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2019 international conference on Machine Learning, Big Data, Cloud and parallel computing, COMITCon 2019

作者： Jangra, Seema Pandit, Amit Kant Gupta, Neha Jain, Ritika Rana, Rishita Department of Electronics Communication Engineering Shri Mata Vaishno Devi University India Computer Science Dept I.P College for Women University of Delhi Delhi India

ISBN: (纸本)9781728102115

Traditional TCP/IP network model needs an end-to-end connection for data transmission. With this traditional network, it is difficult to communicate in those areas where intermittent connectivity exists. Delay Tolerant network (DTN) offers an alternate solution for these challenged areas. In the DTN, end-to-end path between the starting and end node may not be available all the time, but the transfer of data takes place using store-carry-forward technique in which node can depot the data, hold it until another node comes in contact and then deliver it to the destination. DTN with vehicular nodes called Vehicular Delay Tolerant network (VDTN). Here, a comprehensive study of VDTN and comparative study of VDTN routing protocol's performance is done to analyze the effect of size of buffer. The simulation experiment is carried out using ONE simulator with Synthetic Traces and Real Contact Traces. © 2019 IEEE.

关键词： Delay tolerant networks

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Solution of Large-Scale Problems of Global Optimization on the Basis of parallel Algorithms and Cluster Implementation of computing Processes

Solution of Large-Scale Problems of Global Optimization on t...

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10th international conference on parallel computing Technologies

作者： Koshur, Vladimir Kuzmin, Dmitriy Legalov, Aleksandr Pushkaryov, Kirill Siberian Fed Univ Inst Space & Informat Technol Krasnoyarsk 660074 Russia

ISBN: (纸本)9783642032745

The parallel hybrid inverse neural network coordinate approximations algorithm (PHINNCA) for solution of large-scale global optimization problems is proposed in this work. The algorithm maps a trial value of an objective function into values of objective function arguments. It decreases a trial value step by step to find a global minimum. Dual generalized regression neural networks are used to perform the mapping. The algorithm is intended for cluster systems. A search is carried out concurrently. When there are multiple processes, they share the information about their progress and apply a simulated annealing procedure to it.

关键词： optimization global optimization large-scale problems solution cluster neural networks

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Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in parallel computing 31

Broadcast- and Power-Aware Wireless NoC for Barrier Synchron...

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31st IEEE international System on Chip conference, SOCC 2018

作者： Mondal, Hemanta Kumar Cataldo, Rodrigo Cadore Marcon, Cesar Augusto Missio Martin, Kevin Deb, Sujay Diguet, Jean-Philippe Lab-STICC Lorient France Pontifical University of Rio Grande Do sul Brazil IIIT Delhi India

ISBN: (纸本)9781538614907

Efficient synchronization is one of the basic requirements of effective parallel computing. A key operation of the POSIX Thread standard (PThread) is barrier synchronization, where multiple threads block on a user-specified point of execution until all of them have reached it. Conventional architectures for broadcast operations limit the achievable performance benefits as synchronization is significantly affected due to critical path communications. This increases the network latency and degrades the performance dramatically. A Wireless network-on-Chip (WiNoC) offers a promising solution to reduce the long distance/critical path communication bottlenecks of conventional architectures by augmenting them with single hop, long-range wireless links. In this paper, we propose a power-aware broadcast enabled WiNoC architecture to reduce the cost of broadcast operations for barrier-based applications. The proposed architecture reduces the barrier synchronization cost up to 43.97% regarding network latency under the PARSEC benchmarks. It also saves up to 80.49% idle-state power consumption in WIs for a 64-core system compared with the conventional WiNoC architecture without incurring significant overhead. © 2018 IEEE.

关键词： network-on-chip

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