The software complexity in modern vehicle electronic systems is increasingly growing. Vehicle projects have to take into account a growing number of interconnected functions, which are jointly developed by many person...
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ISBN:
(纸本)1402081480
The software complexity in modern vehicle electronic systems is increasingly growing. Vehicle projects have to take into account a growing number of interconnected functions, which are jointly developed by many persons in many different companies. For facing these challenges, new design methodologies for a formalized and partially automated software development are required. The DaVinci design methodology has been developed to match the specific requirements of distributed automotive systems. This includes the function-oriented design of the system structure as well as the deployment on a network and software integration on ECUs (electronic control units). Such a design serves as basis for an automatic code generation process, which integrates the applications into an efficient ECU target architecture with real-time operating system (RTOS) and communication stack. Typical scenarios during the development processes like the reuse, exchange and integration of design data are supported and combined with a flexible configuration management. PC-based test environments may be used for functional integration tests or verification of the network communication. This article is supposed to give a brief overview of the methodology as well as some selected aspects of its implementation in the DaVinci tool suite.
Digital video compression is a computationally intensive task, in which motion estimation accounts for a significant portion of the arithmetic operations. This paper presents ME64, a dedicated scalable hardware archit...
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ISBN:
(纸本)1402081480
Digital video compression is a computationally intensive task, in which motion estimation accounts for a significant portion of the arithmetic operations. This paper presents ME64, a dedicated scalable hardware architecture for fast computation of motion vectors. ME64 is a highly parallel architecture, based on a matrix of 64 processing elements at its core, an I/O interface, and comparison and control units. The proposed architecture was implemented in an FPGA to treat reference and search blocks of 8x8 and 15x15 pixels, respectively. ME64 is scalable to be able to cover larger search blocks if needed. It implements the full search algorithm using the SAD criteria. ME64 was fully described in VHDL and prototyped in the Xilinx XC2S150 FPGA device, with a maximum frequency of 33 MHz. Using this FPGA device, ME64 reaches 2.1 GOps (billions of 8-bit operations per second) and 107.32 frames (640x480 pixels) per second. The results herein presented validate the ME64 against a software implementation, using an external I/O data driver.
The ifiptc-10workingconference on distributed and parallelembeddedsystems (dipes2004) brings together experts from industry and academia to discuss recent developments in this important and growing field in the ...
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ISBN:
(数字)9781402081491
ISBN:
(纸本)9781402081484;9781475780123
The ifiptc-10workingconference on distributed and parallelembeddedsystems (dipes2004) brings together experts from industry and academia to discuss recent developments in this important and growing field in the splendid city of Toulouse, France. The ever decreasing price/performance ratio of microcontrollers makes it economically attractive to replace more and more conventional mechanical or electronic control systems within many products by embedded real-time computer systems. An embedded real-time computer system is always part of a well-specified larger system, which we call an intelligent product. Although most intelligent products start out as stand-alone units, many of them are required to interact with other systems at a later stage. At present, many industries are in the middle of this transition from stand-alone products to networked embeddedsystems. This transition requires reflection and architecting: The complexity of the evolving distributed artifact can only be controlled, if careful planning and principled design methods replace the - hoc engineering of the first version of many standalone embedded products.
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