A single chip that can perform three-channel 1∗4 serial color matrixing, 3∗4 color matrixing, 3∗3 (2-D) convolution, and a nine-TAP FIR filter has been designed in a 1- mu m gate array. The chip operates at 25 MHz and...
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The Hughes imaging Laser Radar sensor gathers separate range and intensity data channels at 2 megabytes/second per channel. Commercially available SIMD parallel processors provide the horsepower to process this data i...
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ISBN:
(纸本)0819407798
The Hughes imaging Laser Radar sensor gathers separate range and intensity data channels at 2 megabytes/second per channel. Commercially available SIMD parallel processors provide the horsepower to process this data in real-time. In this paper we discuss a fairly generic hardware/software architecture to process this data using an APx- 128 SIMD processor for each channel and a 386-based host that provides control of an image display and the recording of features. The expandability and affordability of this approach makes our design applicable to a wide variety of similar problems.
The Conference materials contain 69 papers. Robotic vision systems, machine vision inspection techniques, segmentation of fused range/ intensity imagery, parallel and VLSI architectures for machine vision, comparison ...
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ISBN:
(纸本)0819408735
The Conference materials contain 69 papers. Robotic vision systems, machine vision inspection techniques, segmentation of fused range/ intensity imagery, parallel and VLSI architectures for machine vision, comparison of range segmentation algorithms, state of the arts in post-canny edge detection, simulation and visualization environments for autonomous robots, robot reach/grasp operations, fuzzymorphological neural networks, reasoning techniques for vision systems, recognition techniques, object representation and matching, reactive robotic control strategies, and imageprocessing techniques are the main topics covered.
Several methods of increasing the speed and simplicity of the computation of off-axis transmission holograms are presented, with applications to the real-time display of holographic images. A bipolar intensity approac...
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ISBN:
(纸本)0819408212
Several methods of increasing the speed and simplicity of the computation of off-axis transmission holograms are presented, with applications to the real-time display of holographic images. A bipolar intensity approach enables a linear summation of interference fringes, a factor of two speed increase, and the elimination of image noise caused by object self- interference. An order of magnitude speed increase is obtained through the use of precomputed look-up tables containing a large array of elemental interference patterns corresponding to point source contributions from each of the possible locations in image space. Results achieved using a data-parallel supercomputer to compute horizontal-parallax- only holographic patterns containing 6 megasamples indicate that an image comprised of 10,000 points with arbitrary brightness (grayscale) can be computed in under one second.
Associative processing based on content-addressable memories has been argued to be the natural solution for nonnumerical information processingapplications. Unfortunately, the implementation requirements of these arc...
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Associative processing based on content-addressable memories has been argued to be the natural solution for nonnumerical information processingapplications. Unfortunately, the implementation requirements of these architectures when one uses conventional electronic technology have been cost prohibitive;therefore associative processors have not been realized. Instead, software methods that emulate the behavior of associative processing have been promoted and mapped onto conventional location-addressable systems. However, this does not bring about the natural parallelism of associative processing, namely, the ability to access many data words simultaneously. Optics has the advantage over electronics of directly supporting associative processing by providing economic and efficient interconnects, massive parallelism, and high-speed processing. The principles of designing an optical content-addressable parallel processor (OCAPP) for the efficient support of parallel symbolic computing are presented. The architecture is designed to exploit optics advantages fully in interconnects and high-speed operations. Several parallel search-and-retrieval algorithms are mapped onto an OCAPP to illustrate its capability of supporting parallel symbolic computing. A theoretical performance analysis of these algorithms is presented. This analysis reveals that the execution times of the parallelalgorithms presented are independent of the problem size, which makes the OCAPP suitable for applications in which the number of data sets to be operated on is high (e.g., massive parallelprocessing). A preliminary optical implementation of the architecture with currently available optical components is also presented.
Radar constant false alarm rate (CFAR) detectors are adaptive threshold detectors, used to compensate for unknown noise environments. To normalize mean shifts in this noise level, the system estimates the background n...
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Radar constant false alarm rate (CFAR) detectors are adaptive threshold detectors, used to compensate for unknown noise environments. To normalize mean shifts in this noise level, the system estimates the background noise level in any under-test data sample based on nearby reference data samples, often the surrounding samples. We discuss several advances in the evolution of radar CFAR detectors, from the classical mean-level detector to more recent designs using order statistics, or sorted data values. These algorithms can be implemented by modifying the existing running window order statistics filtering techniques widely used in signal/imageprocessing. Although the signal processing theory of CFAR detection is well advanced, practical applications lag because of the high throughput required in radar. This intensive computational requirement is likely to be met by further advances in VLSI technology alone;it must result from parallelprocessing techniques. Systolic array architectures are proposed for several important CFAR detectors. Techniques for improving the processor utilization efficiency of the proposed array architectures are also discussed.
Adaptive Solutions' CNAPS architecture is a parallel array of digital processors. This design features a Single-Instruction Multiple-Data (SIMD) stream architecture. The architecture is designed to execute on- chi...
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ISBN:
(纸本)0819405515
Adaptive Solutions' CNAPS architecture is a parallel array of digital processors. This design features a Single-Instruction Multiple-Data (SIMD) stream architecture. The architecture is designed to execute on- chip learning for Artificial Neural Network (ANN) algorithms with unprecedented performance. ANNs have shown impressive results for solving difficult imageprocessing tasks. However, current hardware prevents many ANN solutions from being effective products. The CNAPS architecture will provide the computational power to allow real time ANN applications. Because of the high parallelism of the architecture,it is also ideal for digital imageprocessing tasks. This architecture will allow high performance applications that combine conventional imageprocessing methods and ANNs on the same system. This paper gives a brief introduction to the CNAPS architecture, and gives the system performance on implementation of neural network algorithms, and conventional imageprocessingalgorithms such as convolution, and 2D Fourier transforms.
In this paper, the applications of the iterative Gauss-Newton (GN) approach in nonlinear image restoration are considered. The convergence properties of a general class of nonlinear iterative algorithm are studied thr...
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ISBN:
(纸本)0819405515
In this paper, the applications of the iterative Gauss-Newton (GN) approach in nonlinear image restoration are considered. The convergence properties of a general class of nonlinear iterative algorithm are studied through the Global Convergence Theorem (GCT). The iterative GN algorithm for the solution of the least-squares optimization problem is presented. The computational complexity of this algorithm is enormous, making its implementation very difficult in practical applications. Structural modifications are introduced, which drastically reduce the computational complexity while preserving the convergence rate of the GN algorithm. With the structural modifications, the GN algorithm becomes particularly useful in nonlinear optimization problems. The convergence properties of the algorithms introduced are readily derived, on the basis of the generalized analysis and the GCT. The applications of these algorithms on practical problems, is demonstrated through an example.
This paper describes a flexible parallelprocessing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each...
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